High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

 The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%

An Analysis of the Post Quantum and Classical Security of 4x4 and 16x4 S-Boxes and Their Implementations in Simplified-AES

Grover’s algorithm is a quantum searching algorithm that poses a threat to symmetric cryptography. Due to their smaller key sizes, lightweight cryptographic algorithms such as Simplified-AES face a much more immediate threat from Grover’s algorithm than traditional cryptographic algorithms. By analyzing different S-boxes, it was discovered that the S-box 946C753AE8FBD012 may be more quantum resistant than the S-box that Simplified-AES uses, 94ABD1856203CEF7. In addition to this, 16x4 S-boxes (or 4 4x4 S-boxes) showed to be significantly more quantum secure than 4x4 S-boxes. This is because the number of gates needed to model a $2^n$x4 S-box increases at an exponential rate. It was also found that this property extends to $2^n$x8 S-boxes, implying the existence of a more quantum secure 8x8 S-box that AES could use. However, an increase in quantum security does not equate to an increase in classical security, as some of the least quantum secure S-boxes analyzed displayed some of the best classical security. Finally, an alteration of Simplified-AES that used a 16x4 S-box was found that displayed better classical and quantum security than Simplified-AES and did not require an increase in key size

Cellular automata for dynamic S-boxes in cryptography.

In today\u27s world of private information and mass communication, there is an ever increasing need for new methods of maintaining and protecting privacy and integrity of information. This thesis attempts to combine the chaotic world of cellular automata and the paranoid world of cryptography to enhance the S-box of many Substitution Permutation Network (SPN) ciphers, specifically Rijndael/AES. The success of this enhancement is measured in terms of security and performance. The results show that it is possible to use Cellular Automata (CA) to enhance the security of an 8-bit S-box by further randomizing the structure. This secure use of CA to scramble the S-box, removes the 9-term algebraic expression [20] [21] that typical Galois generated S-boxes share. This cryptosystem securely uses a Margolis class, partitioned block, uniform gas, cellular automata to create unique S-boxes for each block of data to be processed. The system improves the base Rijndael algorithm in the following ways. First, it utilizes a new S-box for each block of data. This effectively limits the amount of data that can be gathered for statistical analysis to the blocksize being used. Secondly, the S-boxes are not stored in the compiled binary, which protects against an S-box Blanking [22] attack. Thirdly, the algebraic expression hidden within each galois generated S-box is destroyed after one CA generation, which also modifies key expansion results. Finally, the thesis succeeds in combining Cellular Automata and Cryptography securely, though it is not the most efficient solution to dynamic S-boxes

Advanced approach for encryption using advanced encryption standard with chaotic map

At present, security is significant for individuals and organizations. All information need security to prevent theft, leakage, alteration. Security must be guaranteed by applying some or combining cryptography algorithms to the information. Encipherment is the method that changes plaintext to a secure form called cipherment. Encipherment includes diverse types, such as symmetric and asymmetric encipherment. This study proposes an improved version of the advanced encryption standard (AES) algorithm called optimized advanced encryption standard (OAES). The OAES algorithm utilizes sine map and random number to generate a new key to enhance the complexity of the generated key. Thereafter, multiplication operation was performed on the original text, thereby creating a random matrix (4×4) before the five stages of the coding cycles. A random substitution-box (S-Box) was utilized instead of a fixed S-Box. Finally, we utilized the eXclusive OR (XOR) operation with digit 255, also with the key that was generated last. This research compared the features of the AES and OAES algorithms, particularly the extent of complexity, key size, and number of rounds. The OAES algorithm can enhance complexity of encryption and decryption by using random values, random S-Box, and chaotic maps, thereby resulting in difficulty guessing the original text

Dynamic S-BOX using Chaotic Map for VPN Data Security

A dynamic SBox using a chaotic map is a cryptography technique that changes the SBox during encryption based on iterations of a chaotic map, adding an extra layer of confusion and security to symmetric encryption algorithms like AES. The chaotic map introduces unpredictability, non-linearity, and key dependency, enhancing the overall security of the encryption process. The existing work on dynamic SBox using chaotic maps lacks standardized guidelines and extensive security analysis, leaving potential vulnerabilities and performance concerns unaddressed. Key management and the sensitivity of chaotic maps to initial conditions are challenges that need careful consideration. The main objective of using a dynamic SBox with a chaotic map in cryptography systems is to enhance the security and robustness of symmetric encryption algorithms. The method of dynamic SBox using a chaotic map involves initializing the SBox, selecting a chaotic map, iterating the map to generate chaotic values, and updating the SBox based on these values during the encryption process to enhance security and resist cryptanalytic attacks. This article proposes a novel chaotic map that can be utilized to create a fresh, lively SBox. The performance assessment of the suggested S resilience Box against various attacks involves metrics such as nonlinearity (NL), strict avalanche criterion (SAC), bit independence criterion (BIC), linear approximation probability (LP), and differential approximation probability (DP). These metrics help gauge the Box ability to handle and respond to different attack scenarios. Assess the cryptography strength of the proposed S-Box for usage in practical security applications, it is compared to other recently developed SBoxes. The comparative research shows that the suggested SBox has the potential to be an important advancement in the field of data security.Comment: 11 Page

BBQ: Using AES in Picnic Signatures

This works studies the use of the AES block-cipher for Picnic-style signatures, which work in the multiparty-computation-in-the-head model. It applies advancements to arithmetic circuits for the computation of the AES S-box over multiparty computation in the preprocessing model to obtain an improvement of signature sizes of 40\% on average compared to using binary circuits for AES-128, AES-192 and AES-256 in combination with previous techniques. This work also discusses other methods for the computation of the S-box and provides insights into the reaches and limits of the multiparty-computation-in-the-head paradigm

Matrix Power S-Box Construction

The new symmetric cipher S-box construction based on matrix power function is presented. The matrix consisting of plain data bit strings is combined with three round key matrices using arithmetical addition and exponent operations. The matrix power means the matrix powered by other matrix. The left and right side matrix powers are introduced. This operation is linked with two sound one-way functions: the discrete logarithm problem and decomposition problem. The latter is used in the infinite non-commutative group based public key cryptosystems. It is shown that generic S-box equations are not transferable to the multivariate polynomial equations in respect of input and key variables and hence the algebraic attack to determine the key variables cannot be applied in this case. The mathematical description of proposed S-box in its nature possesses a good ``confusion and diffusion\u27\u27 properties and contains variables ``of a complex type\u27\u27 as was formulated by Shannon. Some comparative simulation results are presented

Towards the Reverse-Engineering of the CaveTable

International audienceThis report focuses on the S-Box used in CMEA . The purpose is to find the generation process of this S-Box. Such knowledge is important since a weak design process usually results in vulnerability against attacks. Many of them have already been published against CMEA. The attackers used the statistical bias in the S-Box to develop their attack. We want to know what caused such a statistical bias, so that this methodmay be avoided later on. In order to find a structure in this S-Box, we first recall the high level structure that has already been found before. We then look at several properties, such as the linear and differential properties and the hardware related properties, and finally, the relations with other cryptographic algorithms. Our results show that the TU structure is likely just a consequence of the S-Box being generated from thirty-two4×4 permutations being concatenated. The properties of the tables components involved in the structure are all consistent with those of pseudo-random permutations. Hence, the S-Box might just be constructed using thirty-two pseudo- randomly generated4×4 permutations

Improving Hardware Implementation of Cryptographic AES Algorithm and the Block Cipher Modes of Operation

With ever increasing Internet traffic, more business and financial transactions are being conducted online. This is even more so during these days of COVID-19 pandemic when traditional businesses such as traditional face to face educational systems have gone online requiring huge amount of data being exchanged over Internet. Increase in the volume of data sent over the Internet has also increased the security vulnerabilities such as challenging the confidentiality of data being sent over the Internet. Due to sheer volume, all data will need to be effectively encrypted. Due to increase in the volume of data, it is also important to have encryption/decryption functions to work at a higher speed to maintain the confidentiality of sensitive data. In this thesis, our goal is to enhance the hardware speed of encryption process of the standard AES scheme and its four variants such as AES-128, AES-192, AES-256 and new AES-512 and implement such functions on an FPGA. We also consider the FPGA implementation of different modes of AES operation. By employing parallelism and pipelining approach, we attempt to speed up various computational components of AES implementations using the Quartus II onto Intel’s FPGA. This approach shows improvement in the response speed, data throughput and latency