Output-Capacitorless CMOS LDO Regulator Based on High Slew-Rate Current-Mode Transconductance Amplifier

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF.Postprint (published version

An ultra-low-voltage class-AB OTA exploiting local CMFB and body-to-gate interface

In this work a novel bulk-driven (BD) ultra-low-voltage (ULV) class-AB operational transconductance amplifier (OTA) which exploits local common mode feedback (LCMFB) strategies to enhance performance and robustness against process, voltage and temperature (PVT) variations has been proposed. The amplifier exploits body-to-gate (B2G) interface to increase the slew rate and attain class-AB behaviour, whereas two pseudo-resistors have been employed to increase the common mode rejection ratio (CMRR). The architecture has been extensively tested through Monte Carlo and PVT simulations, results show that the amplifier is very robust in terms of gain-bandwidth-product (GBW), power consumption and slew rate. A wide comparison against state-of-the-art has pointed out that best small-signal figures of merit are attained and good large-signal performance is guaranteed, also when worst-case slew rate is considered

CMOS operational amplifiers with continuous-time capacitive common mode feedback

A simple and power efficient approach for the implementation of continuous-time common mode feedback networks using a capacitive averaging network is introduced. It is shown that low voltage, continuous-time, fully differential rail to rail operation can be achieved using the proposed technique. This at the expense of very small additional hardware and no additional power dissipation One stage, two stage, telescopic and folded cascode op-amps are discussed as application examples

High-precision fluorescence photometry for real-time biomarkers detection

Les derniers évènements planétaires et plus particulièrement l'avènement sans précédent du nouveau coronavirus augmente la demande pour des appareils de test à proximité du patient. Ceux-ci fonctionnent avec une batterie et peuvent identifier rapidement des biomarqueurs cibles. Pareils systèmes permettent aux utilisateurs, disposant de connaissances limitées en la matière, de réagir rapidement, par exemple dans la détection d'un cas positif de COVID-19. La mise en œuvre de l'élaboration d'un tel instrument est un projet multidisciplinaire impliquant notamment la conception de circuits intégrés, la programmation, la conception optique et la biologie, demandant tous une maîtrise pointue des détails. De plus, l'établissement des spécifications et des exigences pour mesurer avec précision les interactions lumière-échantillon s'additionnent au besoin d'expérience dans la conception et la fabrication de tels systèmes microélectriques personnalisés et nécessitent en elles-mêmes, une connaissance approfondie de la physique et des mathématiques. Ce projet vise donc à concevoir et à mettre en œuvre un appareil sans fil pour détecter rapidement des biomarqueurs impliqués dans des maladies infectieuses telles que le COVID-19 ou des types de cancers en milieu ambulatoire. Cette détection se fait grâce à des méthodes basées sur la fluorescence. La spectrophotométrie de fluorescence permet aux médecins d'identifier la présence de matériel génétique viral ou bactérien tel que l'ADN ou l'ARN et de les caractériser. Les appareils de paillasse sont énormes et gourmand énergétiquement tandis que les spectrophotomètres à fluorescence miniatuarisés disponibles dans le commerce sont confrontés à de nombreux défis. Ces appareils miniaturisés ont été découverts en tirant parti des diodes électroluminescentes (DEL) à semi-conducteurs peu coûteuses et de la technologie des circuits intégrés. Ces avantages aident les scientifiques à réduire les erreurs possibles, la consommation d'énergie et le coût du produit final utilisé par la population. Cependant, comme leurs homologues de paillasse, ces appareils POC doivent quantifier les concentrations en micro-volume d'analytes sur une large gamme de longueurs d'onde suivant le cadre d'une économie en ressources. Le microsystème envisagé bénéficie d'une approche de haute précision pour fabriquer une puce microélectronique CMOS. Ce procédé se fait de concert avec un boîtier personnalisé imprimé en 3D pour réaliser le spectrophotomètre à la fluorescence nécessaire à la détection quantitative d'analytes en microvolume. En ce qui a trait à la conception de circuits, une nouvelle technique de mise à auto-zeroing est appliquée à l'amplificateur central, celui-ci étant linéarisé avec des techniques de recyclage et de polarisation adaptative. Cet amplificateur central est entièrement différentiel et est utilisé dans un amplificateur à verrouillage pour récupérer le signal d'intérêt éclipsé par le bruit. De plus, l'augmentation de la sensibilité de l'appareil permet des mesures quantitatives avec des concentrations en micro-volume d'analytes ayant moins d'erreurs de prédiction de concentration. Cet avantage cumulé à une faible consommation d'énergie, un faible coût, de petites dimensions et un poids léger font de notre appareil une solution POC prometteuse dans le domaine de la spectrophotométrie de fluorescence. La validation de ce projet s'est fait en concevant, fabriquant et testant un prototype discret et sans fil. Son article de référence a été publié dans IEEE LSC 2018. Quant à la caractérisation et l'interprétation du prototype d'expériences in vitro à l'aide d'une interface MATLAB personnalisée, cet article a été publié dans IEEE Sensors journal (2021). Les circuits intégrés et les photodétecteurs ont été fabriqués ont été conçus et fabriqués par Cadence en 2019. Relativement aux solutions de circuit proposées, elles ont été fabriquées avec la technologie CMOS 180 nm et publiées lors de la conférence IEEE MWSCAS 2020. Tout comme cette dernière contribution, les expériences in vitro avec le dispositif proposé incluant la puce personnalisée et le boîtier imprimé en 3D ont été réalisés et les résultats électriques et optiques ont été soumis au IEEE Journal of Solid-State Circuits (JSSC 2022).The most recent and unprecedented experience of the novel coronavirus increases the demand for battery-operated near-patient testing devices that can rapidly identify the target biomarkers. Such systems enable end-users with limited resources to quickly get feedback on various medical tests, such as detecting positive COVID-19 cases. Implementing such a device is a multidisciplinary project dealing with multiple areas of expertise, including integrated circuit design, programming, optical design, and biology, each of which needs a firm grasp of details. Alongside the need for experience in designing and manufacturing custom microelectronic systems, establishing the specifications and requirements to precisely measure the light-sample interactions requires an in-depth knowledge of physics and mathematics. This project aims to design and implement a wireless point-of-care (POC) device to rapidly detect biomarkers involved in infectious diseases such as COVID-19 or different types of cancers in an ambulatory setting using fluorescence-based methods. Fluorescence spectrophotometry allows physicians to identify and characterize viral or bacterial genetic materials such as DNAs or RNAs. The benchtop devices that are currently available are bulky and power-hungry, whereas the commercially available miniaturized fluorescence spectrophotometers are facing many challenges. Many of these difficulties have been resolved in literature thanks to inexpensive semiconductor light-emitting diodes (LEDs) and integrated circuits technology. Such advantages aid scientists in decreasing the size, power consumption, and cost of the final product for end-users. However, like the benchtop counterparts, such POC devices must quantify micro-volume concentrations of analytes across a wide wave length range under an economy of resources. The envisioned microsystem benefits from a high-precision approach to fabricating a CMOS microelectronic chip combined with a custom 3D-printed housing. This implementation results in a fluorescence spectrophotometer for qualitative and quantitative detection of micro-volume analytes. In terms of circuit design, a novel switched-biasing ping-pong auto-zeroed technique is applied to the core amplifier, linearized with recycling and adaptive biasing techniques. The fully differential core amplifier is utilized within a lock-in amplifier to retrieve the signal of interest overshadowed by noise. Increasing the device's sensitivity allows quantitative measurements down to micro-volume concentrations of analytes with less concentration prediction error. Such an advantage, along with low-power consumption, low cost, low weight, and small dimensions, make our device a promising POC solution in the fluorescence spectrophotometry area. The approach of this project was validated by designing, fabricating, and testing a discrete and wireless prototype. Its conference paper was published in IEEE LSC 2018, and the prototype characterization and interpretation of in vitro experiments using a custom MATLAB interface were published in IEEE Sensors Journal (2021). The integrated circuits and photodetectors were designed and fabricated by the Cadence circuit design toolbox (2019). The proposed circuit solutions were fabricated with 180-nm CMOS technology and published at IEEE MWSCAS 2020 conference. As the last contribution, the in vitro experiments with the proposed device, including the custom chip and 3D-printed housing, were performed, and the electrical and optical results were submitted to the IEEE Journal of Solid-State Circuits (JSSC 2022)

Performance enhancement techniques for operational amplifiers

Operational amplifiers (op amps) are one of the most fundamental and widely used building blocks for analog and mixed-signal circuits and systems. As transistors’ feature size scales down in the deep submicron process, the short channel effects, high leakage current and reduced supply voltages make the design of op amps more challenging. In this dissertation, we present several methods to improve op amps’ DC gain, slew rate, power efficiency and current utilization efficiency (CUE). A basic requirement for an op amp is high DC gain especially for high precision applications. We introduce a method to robustly improve op amps’ DC gain with negligible power and area overhead. The new DC gain enhancement method can be implemented based on the source degeneration circuit (SDC) or the flipped voltage attenuator (FVA). Compared to the FVA-based technique, the SDC-based technique is more suitable for those CMOS processes whose transistors’ threshold voltages are too low for the transistors in the FVA to work in weak or strong inversion regions. Otherwise, the FVA-based technique is recommended as this technique is more robust to devices’ random mismatch. A prototype op amp with the FVA-based technique is designed and fabricated in the IBM130nm process. The measurement and simulation results of the prototype verify that the technique largely enhances an op amp’s DC and is very robust over process, voltage and temperature variations. Another important op amp requirement is high slew rate. In this regard, we introduce a method that greatly improves an op amp’s slew rate while still preserving its small signal performance by a well-defined turn-on condition. The performance of the introduced method is discussed in comparison with an existing adaptive biasing method that was widely used to enhance slew rate. The introduced method excels in several aspects. First, unlike the adaptive biasing method which degrades an op amp’ linearity, the introduced method is able to enhance linearity. Second, the proposed method improves an op amp’s slew rate by 2320% (vs. 780% by the adaptive method) with the power and area overhead of 2% and 1.2% (vs. 15% and 35% by the adaptive method). In addition, the proposed method improves the op amp’s total harmonic distortion (THD) by 6dB but the adaptive method degrades the THD by 12dB. The ability to drive large capacitive loads is becoming critical for op amps in emerging applications such as liquid crystal display drivers. In this regard, we introduce a power efficient design of op amps that can drive large capacitive loads. The proposed method decouples the large and small signal performance, eliminates current waste in the preamp stages’ load circuits, and is not sensitive to devices’ random mismatches. Compared to the state-of-the-art methods, our design prototype in a CMOS 180nm process shows largely improved small and large signal figure of merits, equivalent to largely improved power efficiency for given small and large signal performance specifications. Folded cascode amplifier (FCA) is a commonly used architecture for designing op amps, but a significant portion of supply current is wasted in the cascode stage. This not only reduces the current utilization efficiency (CUE), defined as the ratio of an FCA’s tail current to its total supply current, but also degrades the FCA’s gain, noise and offset. In this regard, we introduce a method to dramatically reduce a FCA’s cascode stage current without degrading the FCA’s settling performance. Compared to the existing methods, the proposed method effectively improves not only the CUE but also the settling performance of op amps. Lastly, a prototype FCA, with the proposed performance enhancement techniques of gain, slew rate and CUE, is designed to demonstrate the compatibility of these techniques

Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor

Due to the switch from CCD to CMOS technology, CMOS based image sensors have become smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart from the extensive set of applications requiring image sensors, the next technological breakthrough in imaging would be to consolidate and completely shift the conventional CMOS image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative technology in the imaging field, allowing multiple silicon tiers with different functions to be stacked on top of each other. The technology allows for an extreme parallelism of the pixel readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked image sensor, and the parallelism of the readout can remain constant at any spatial resolution of the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor array resolution. The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked image sensors, structured with parallel readout circuitries. The readout circuit’s key requirements are low noise, speed, low-area (for higher parallelism), and low power. A CMOS imaging review is presented through a short historical background, followed by the description of the motivation, the research goals, and the work contributions. The fundamentals of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features, the essential building blocks, types of operation, as well as their physical characteristics and their evaluation metrics. Following up on this, the document pays attention to the readout circuit’s noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron noise imagers. Lastly, the fabricated test CIS device performances are reported along with conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de imagens, virtualmente para qualquer resolução desejada. O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído, planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído, rapidez e pouca área utilizada, de forma a obter-se o melhor rácio. Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos de operação, assim como as suas características físicas e suas métricas de avaliação. No seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões, terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto com o possível trabalho futuro

Output-Capacitorless CMOS LDO Regulator Based on High Slew-Rate Current-Mode Transconductance Amplifier

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF

Output–Capacitorless CMOS LDO Regulator Based on High Slew–rate current-mode transconductance amplifier

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 µm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF