ROCOV scheme for Fault Detection and Location in HVDC sytems

A reliable DC fault protection system is essential for the development of HVDC grids. Therefore, this paper deals with the voltage derivative ROCOV scheme to locate and detect DC faults. The algorithm is able to differentiate internal and external faults considerably fast. The proposed algorithm is analyzed in a HVDC grid with different fault case scenarios. Finally, the ROCOV protection thresholds are discussed.The authors thank the support from the Spanish Ministry of Economy, Industry and Competitiveness (project ENE2016-79145-R AEI/FEDER, UE) and GISEL research group IT1083-16), as well as from the University of the Basque Country UPV/EHU (research group funding PPG17/23)

Fault protection with a digital computer

A fundamental basis has been developed for the use of a time-shared stored-program digital computer to perform many of the electrical power-system protective-relay functions in a substation. Logic operations are given to detect a fault, locate it and initiate the opening of the appropriate circuit breakers, whether the fault is in the station or on lines radiating from the station. The instantaneous value of the station voltages and currents are sampled at a 0.5 ms rate, converted to digital form and stored for computer main-frame use. Operating times are compatible with the 25 ms breaker trip capability of modern two-cycle breakers. Computer speed in initiating tripping is a maximum of 4 ms for severe faults and a maximum of 10 ms for moderate or distant faults. Little attention has been given to hardware or programming aspects; instead this treatment represents the viewpoint of a protective-relay engineer who is attempting to answer the question: can it be done and what is involved? However, major emphasis was placed on minimizing computer main-frame duty

The Test Bench for Simulation Phase Fault and Ground Fault Analysis Protection Concept Using Symmetrical Components

Various laboratory experiment platforms have been developed to provide students with theoretical knowledge and practical experience. Understanding concepts related to the process for determining the design of protection settings requires practical experience, which can be achieved by repeated trials. In this paper, the mechanism of a ground fault in a medium voltage feeder is done using a simulator substation as a case study. This process must be carried out twice, once for the ground-fault relays protection based on residual currents and then repeated based on residual voltage. For further understanding of the electrical distribution network, the system will be operated at 20 kV on the primary and 380 V on the secondary. The model uses smaller nominal voltages consisting of 380 V on the primary and the secondary. The result of one phase fault protection mechanism works well at each point of interference, and voltage transformers are protected from overheating and damage. The lowest value of the single-phase to ground short circuit that occurs at the fault location at the farthest point of interference from the protection relay location is used for the threshold setting on the voltage relay. The one phase fault protection mechanism works well at each point of interference, and the voltage transformer is protected from overheating and damage. For residual current ground fault protection effective, the threshold setting of phase fault inverse time delay with threshold setting I> is 1.5 ampere, and instantaneous I>> is 7.5 ampere. The effective threshold setting for residual ground fault protection wasUo> = 22% dan UO>> = 33,2%

Space station common module network topology and hardware development

Conceptual space station common module power management and distribution (SSM/PMAD) network layouts and detailed network evaluations were developed. Individual pieces of hardware to be developed for the SSM/PMAD test bed were identified. A technology assessment was developed to identify pieces of equipment requiring development effort. Equipment lists were developed from the previously selected network schematics. Additionally, functional requirements for the network equipment as well as other requirements which affected the suitability of specific items for use on the Space Station Program were identified. Assembly requirements were derived based on the SSM/PMAD developed requirements and on the selected SSM/PMAD network concepts. Basic requirements and simplified design block diagrams are included. DC remote power controllers were successfully integrated into the DC Marshall Space Flight Center breadboard. Two DC remote power controller (RPC) boards experienced mechanical failure of UES 706 stud-mounted diodes during mechanical installation of the boards into the system. These broken diodes caused input to output shorting of the RPC's. The UES 706 diodes were replaced on these RPC's which eliminated the problem. The DC RPC's as existing in the present breadboard configuration do not provide ground fault protection because the RPC was designed to only switch the hot side current. If ground fault protection were to be implemented, it would be necessary to design the system so the RPC switched both the hot and the return sides of power

Methodology for Designing Fault-Protection Software

A document describes a methodology for designing fault-protection (FP) software for autonomous spacecraft. The methodology embodies and extends established engineering practices in the technical discipline of Fault Detection, Diagnosis, Mitigation, and Recovery; and has been successfully implemented in the Deep Impact Spacecraft, a NASA Discovery mission. Based on established concepts of Fault Monitors and Responses, this FP methodology extends the notion of Opinion, Symptom, Alarm (aka Fault), and Response with numerous new notions, sub-notions, software constructs, and logic and timing gates. For example, Monitor generates a RawOpinion, which graduates into Opinion, categorized into no-opinion, acceptable, or unacceptable opinion. RaiseSymptom, ForceSymptom, and ClearSymptom govern the establishment and then mapping to an Alarm (aka Fault). Local Response is distinguished from FP System Response. A 1-to-n and n-to- 1 mapping is established among Monitors, Symptoms, and Responses. Responses are categorized by device versus by function. Responses operate in tiers, where the early tiers attempt to resolve the Fault in a localized step-by-step fashion, relegating more system-level response to later tier(s). Recovery actions are gated by epoch recovery timing, enabling strategy, urgency, MaxRetry gate, hardware availability, hazardous versus ordinary fault, and many other priority gates. This methodology is systematic, logical, and uses multiple linked tables, parameter files, and recovery command sequences. The credibility of the FP design is proven via a fault-tree analysis "top-down" approach, and a functional fault-mode-effects-and-analysis via "bottoms-up" approach. Via this process, the mitigation and recovery strategy(s) per Fault Containment Region scope (width versus depth) the FP architecture

Hardware implementation of series DC arc fault protection using fast Fourier transform

This paper proposes method of series DC arc fault protection using low cost microcontroller. Series DC arc fault occurs when gap between conductor or wire flows a current. Series DC arc fault can cause fire hazard if do not detected and protected. However, Series DC arc fault is difficult to detected using conventional protection. To detect series DC arc fault accurately using fast Fourier transform (FFT). FFT is used to transform signal in time domain to frequency domain. Series DC arc fault has different characteristic compared by normal current in frequency domain. Therefore, the proposed algorithm for protection of series DC arc fault based on magnitudes of the current in frequency domain. Hardware system is implemented by 100 V DC power supply and DC arc fault generator. Test result is conducted experimentally under varying of load current such as 2 A, 2.5 A, 3 A, 3.5 A, 4 A and 5 A. Experimental testing results show that Series DC arc fault protection has time for trip of 0.48 s, 0.26 s, 1.04 s, 0.68 s, 0.44 s and 0.48, respectively. The fastest time for trip is 0.26 s with current of 2.5 A. Therefore, the proposed algorithm for series DC arc fault protection can operate to trip accurately and have the good performance

Havens: Explicit Reliable Memory Regions for HPC Applications

Supporting error resilience in future exascale-class supercomputing systems is a critical challenge. Due to transistor scaling trends and increasing memory density, scientific simulations are expected to experience more interruptions caused by transient errors in the system memory. Existing hardware-based detection and recovery techniques will be inadequate to manage the presence of high memory fault rates. In this paper we propose a partial memory protection scheme based on region-based memory management. We define the concept of regions called havens that provide fault protection for program objects. We provide reliability for the regions through a software-based parity protection mechanism. Our approach enables critical program objects to be placed in these havens. The fault coverage provided by our approach is application agnostic, unlike algorithm-based fault tolerance techniques.Comment: 2016 IEEE High Performance Extreme Computing Conference (HPEC '16), September 2016, Waltham, MA, US

A system architecture for a planetary rover

Each planetary mission requires a complex space vehicle which integrates several functions to accomplish the mission and science objectives. A Mars Rover is one of these vehicles, and extends the normal spacecraft functionality with two additional functions: surface mobility and sample acquisition. All functions are assembled into a hierarchical and structured format to understand the complexities of interactions between functions during different mission times. It can graphically show data flow between functions, and most importantly, the necessary control flow to avoid unambiguous results. Diagrams are presented organizing the functions into a structured, block format where each block represents a major function at the system level. As such, there are six blocks representing telecomm, power, thermal, science, mobility and sampling under a supervisory block called Data Management/Executive. Each block is a simple collection of state machines arranged into a hierarchical order very close to the NASREM model for Telerobotics. Each layer within a block represents a level of control for a set of state machines that do the three primary interface functions: command, telemetry, and fault protection. This latter function is expanded to include automatic reactions to the environment as well as internal faults. Lastly, diagrams are presented that trace the system operations involved in moving from site to site after site selection. The diagrams clearly illustrate both the data and control flows. They also illustrate inter-block data transfers and a hierarchical approach to fault protection. This systems architecture can be used to determine functional requirements, interface specifications and be used as a mechanism for grouping subsystems (i.e., collecting groups of machines, or blocks consistent with good and testable implementations)

DC fault protection strategy considering DC network partition

This paper investigates DC network partition and alternative DC fault protection strategy for Multi-terminal HVDC (MTDC) system. Fast acting DC Circuit Breakers (DCCBs) or fault blocking DC-DC converters can be configured at strategic locations to allow the entire MTDC system to be operated interconnected but partitioned into islanded DC network zones following faults. In case of any DC fault event, the DCCBs or DC-DC converters at the strategic cable connections that link the different DC network partitions are opened or blocked such that the faulty DC network zone is quickly isolated from the remaining of the MTDC system. Thus, the healthy DC network zone can remain operational or recover quickly to restore power transmission. Each DC zone can be protected using AC circuit breakers and DC switches for cost reduction. The validity of the proposed protection strategy is confirmed using MATLAB/SIMULINK simulation