Design techniques for high performance asynchronous arithmetic operators

High performance asynchronous arithmetic operator design techniques are proposed, which adopt some of the techniques commonly used in synchronous systems such as fast precharged logic and efficient latch design, while maintaining the features of localized and elastic pipelining control inherent in asynchronous design. A pipelined sixteen bit multiplier designed using these techniques is presented and its performance compared with several previously reported asynchronous and synchronous designs

NAND Flash Memory Characterization

The NAND technology has become a popular research area and implementation choice due to its non-volatile flash memory characteristics. There are many engineering challenges when it comes to NAND technology. Some of the limiting factors are reducing the transistor width and increasing read and write performance. The device physics for NAND floating gate cell technology also introduces challenges. Using a floating gate transistor that can address up to 4 bits per cell allows for higher density. However, this introduces a higher internal current leakage that can cause read and program inaccuracies. With floating-gate 3D NAND technology, we are able to better the data retention and have better QLC (Quad-Level Cell) capability. 3D NAND technology has a series of memory cells interconnected that can achieve higher data density and increased storage capacity. In this research, the Gen-4 NAND Flash device functionality is explored by design validation to achieve higher solid-state drive performance. This technology is 144-Layer QLC NAND Flash which is 1024Gb in density. My contributions are implemented showing improved read and write performance for customer operations and how inaccuracies are dealt with from a software and hardware perspective. Silicon wafer testing is also explored to fully characterize and analyze the problem

EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to balance timing bud- gets of critical paths for each individual chip after manufacturing. The challenge of this method is that path delays should be mea- sured for each chip to configure the tuning buffers properly. Current methods for this delay measurement rely on path-wise frequency stepping. This strategy, however, requires too much time from ex- pensive testers. In this paper, we propose an efficient delay test framework (EffiTest) to solve the post-silicon testing problem by aligning path delays using the already-existing tuning buffers in the circuit. In addition, we only test representative paths and the delays of other paths are estimated by statistical delay prediction. Exper- imental results demonstrate that the proposed method can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201

The On-orbit Calibrations for the Fermi Large Area Telescope

The Large Area Telescope (LAT) on--board the Fermi Gamma ray Space Telescope began its on--orbit operations on June 23, 2008. Calibrations, defined in a generic sense, correspond to synchronization of trigger signals, optimization of delays for latching data, determination of detector thresholds, gains and responses, evaluation of the perimeter of the South Atlantic Anomaly (SAA), measurements of live time, of absolute time, and internal and spacecraft boresight alignments. Here we describe on orbit calibration results obtained using known astrophysical sources, galactic cosmic rays, and charge injection into the front-end electronics of each detector. Instrument response functions will be described in a separate publication. This paper demonstrates the stability of calibrations and describes minor changes observed since launch. These results have been used to calibrate the LAT datasets to be publicly released in August 2009.Comment: 60 pages, 34 figures, submitted to Astroparticle Physic

Matrix multiplication using quantum-dot cellular automata to implement conventional microelectronics

Quantum-dot cellular automata (QCA) shows promise as a post silicon CMOS, low power computational technology. Nevertheless, to generalize QCA for next-generation digital devices, the ability to implement conventional programmable circuits based on NOR, AND, and OR gates is necessary. To this end, we devise a new QCA structure, the QCA matrix multiplier (MM), employing the standard Coulomb blocked, five quantum dot (QD) QCA cell and quasi-adiabatic switching for sequential data latching in the QCA cells. Our structure can multiply two N x M matrices, using one input and one bidirectional input/output data line. The calculation is highly parallelizable, and it is possible to achieve reduced calculation time in exchange for increasing numbers of parallel matrix multiplier units. We show convergent, ab initio simulation results using the Intercellular Hartree Approximation for one, three, and nine matrix multiplier units. The structure can generally implement any programmable logic array (PLA) or any matrix multiplication based operation.Comment: 14 pages, 9 figures, supplemental informatio

A solution for improved simulation efficiency of a multi-domain marine power system model

Integrated Full Electric Propulsion (IFEP) marine power systems offer increased design flexibility and operational economy by supplying ship propulsion and service loads from a common electrical system. Predicting the behaviour of IFEP systems through simulation is important in reducing the design risk. However, the prevalence of power electronics and the potential for interaction between large electrical and mechanical systems introduce significant simulation challenges. This paper presents an integrated simulation tool, which brings together electrical, mechanical, thermal and hydrodynamic models, facilitating a holistic simulation capability. Approaches adopted for model validation and computational efficiency together with two case studies are discussed

An 180 MHz 16 bit multiplier using asynchronous logic design techniques

A CMOS digital logic design technique is described which exploits the advantages of fast precharged logic and efficient latch design commonly used in synchronous systems while maintaining the features of localized control inherent in asynchronous design. A pipelined sixteen bit multiplier is presented and its performance compared with several previously reported asynchronous and synchronous designs