Matveev, M

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Implementation of the Sorting Schemes in a Programmable LogicMatveev, M.Rice University,  Houston, TX  77005  USAmatveev@physics.rice.eduAbstractExperiments at the Large Hadron Collider(LHC) at CERN  require a sophisticated  multi-level trigger systems for data selection.  At theCompact Muon Solenoid (CMS) experiment,the main task of Level 1 Trigger is to reduce thefrequency of events from 40MHz down to100kHz [1]. There are three major muonsubsystems at the CMS: Cathode Strip Chambers(CSC), Drift Tubes (DT), and Resistive PlateChambers (RPC).  The Level 1 decision shouldbe made  about 3 µs after an interaction in thecollision area, so only  simple algorithmsimplemented in hardware can be used at thislevel.    The current design requires that only the fourbest trigger candidates from each muonsubsystem be passed to  the Global MuonTrigger  (GMT) System. It is considered thatthere is a sorter at the upper level of each muonsubsystem trigger chain, which selects the fourbest candidates out of  several tens of  incomingand transmits them to the GMT. We propose afast and flexible solution which would allow theimplementation  of such sorters for the variousCMS muon subsystems. Four sorting schemes “3objects out of 18”, “4 objects out of 8”,  “4objects out of 24” and “4 objects out of 36” arediscussed. The first one is intended for the MuonPort Card [2] being designed for the CSCTrigger Electronics. The second scheme can beused for the RPC Sorting Processor [3]. Thethird scheme can be used for the DT MuonSorter [4]. The fourth scheme is targeted to CSCMuon Sorter [2].  Designs  based on Altera20KE [5] Programmable Logic Devices (PLD)and results of simulation are presented.I. DESIGN ASSUMPTIONSWe assume that sorting is based on the valueof input patterns: higher ranks correspond to“better” patterns for the purpose of sorting. Allschemes are targeted to a single chipimplementation in order to reduce the overallsorting time. Each sorter chip receives 8, 18, 24or 36  input patterns and outputs an addresses ofthree or four best patterns. The addresses ofincoming patterns are assigned inside the sorterchip for the first, third and fourth schemes andobtained from the outer logic for the secondscheme. If sorting objects contain more  bits thanthe patterns that are used for the sorting, theyshould be  temporarily pipelined in the externalregisters, and  the addresses of the best  patternscan be used for their  further multiplexing ontooutputs of the sorter board. This pipelining aswell as a sorting logic can be done in a singlechip if it has a sufficient number of  input andoutput pins.    We have implemented our sortingschemes for the 7- and 8-bit patterns, which istypical for the CMS muon trigger systems.We assume that all patterns come to thesorter device in parallel being synchronized withits master clock. The input and output latches forall patterns and their addresses provide a reliablesynchronous  operation and predictable timing.All our designs are targeted to applications at theLHC experiments, where the main operatingclock frequency is 40.08Mhz, so our goal was toachieve a registered performance of  40+ MHzfor all sorting schemes with the minimal latency.Finally we assume that all inputs are not pre-selected (or ranked), but all the output patternsshould be ranked, or present on the outputs of thesorter chip  in descending order.II. TARGETED  DEVICES AND DESIGNSOFTWAREThe main requirements  for the targeteddevices  are:  (1) they should be fast and flexibleenough to be able to implement sorting schemesin a few  clock cycles of the 40MHz clock  and(2) provide an adequate number of input andoutput pins for a single-chip implementation.One approach is to develop and  use an ASICs.Another approach assumes utilization of  PLD,or Field Programmable Gate Arrays (FPGA). Sofar ASICs have an inherent speed advantage overa PLD or FPGA due to their dedicated metalrouting. Soft routing of PLD/FPGA makes themrun slower than  an ASIC. But the gap betweenASIC and PLD/FPGA performance is decreasingdue to advances in technology and chiparchitecture. The important advantages of usingPLD/FPGA are the low nonrecurringengineering fees, reprogrammable features  aswell as a shorter design cycle. Due to thesefactors we focus on using of the PLD/FPGAdevices for our designs. The Xilinx Virtex-E [6]and Altera 20KE [5] families are the mostattractive for our needs  due to their highperformance and great flexibility. Our designsare targeted to Altera 20KE devices.  We haveused an  Altera Quartus version 2000.05 PLDdesign software running on a PC.III. SORTING   METHODWe  perform all necessary comparisons inparallel at the beginning  of the sorting process.In case of (n) input patterns the total number ofcomparisons between all patterns is N=n(n-1)/2.These numbers  N are 28, 153, 276 and 630 forn=8, 18, 24 and 36 respectively.  N results of  allcomparisons would allow us to obtain (4n)combinatorial signals for the addressmultiplexing onto chip outputs. In case of “4objects out of  8” scheme the four best patternsalong with their addresses are transmitted to thechip outputs. Simplified block diagram of thesorting scheme for n=18 is shown on Figure 1.For all our designs, if a few equal patterns areselected, the pattern with the largest addressreceives the highest rank.Figure 1:   Sorting Scheme  “3 objects  out of 18”IV. RESULTS  OF  SIMULATIONThe results of simulation are shown in Table1. All timing parameters are obtained for thefastest (-1 speed grade) devices.  The sortingschemes “4 out of 24” and “4 out of 36”  areimplemented in two and four  clock cyclesrespectively and both require  an intermediateflip-flops (FF).We assume that the actual sorting latency (inclock cycles or nanoseconds) means the timeinterval  between the latching of the inputpatterns into  sorter  chip  and  moment when theselected addresses  and in some cases also thebest patterns are available for latching in theexternal register outside the sorter chip.Additional time is needed for the output datalatching in the external registers to assurereliable synchronous operation. This time shouldbe added to the internal latency parameter inTable 1 in order to obtain an actual latency ofeach sorting scheme. According to the timingmodel of  the fastest devices in 20KE family [5],the maximum clock-to-output delay Toutco withENCODEDADDRESSESMUX1MUX2MUX318 PATTERNS1531818181st  BEST ADD2nd  BEST ADD3rd  BEST ADDFFFFFFFFALLCOMPARISONSSELECTTHIRDBESTSELECTSECONDBESTSELECTFIRSTBESTthe global clock at the input/output register isless than 5 ns. The propagation delay betweenthe sorter PLD and  destination device as well assetup  time  for  the destination device shouldalso be taken into account.  ClockShift circuitry[5] available in 20KE devices can provide anoutput clock signal shifted with respect to theinput clock. Particularly, the output clock withphase shift of 180 degrees (half of period of the40MHz clock, or 12.5 ns) can be used for theoutput data latching  into the external register.Table 1: Results  of  SimulationSorting Scheme 3 out of  18 4 out of  8 4 out of  24 4 out of  36Number of inputs (except clock) 8*18=144 (8+8)*8=128 7*24=168 7*36=252Number of outputs 5*3=15 (8+8)*4=64 5*4=20 6*4=24Altera  PLD  Device EP20K100EFC324-1EP20K60EFC324-1EP20K200EFC484-1EP20K400EFC672-1Internal latency,  clock cycles of  40MHz 1 1 2 4Maximum registered performance, MHz 43.62 68.25 41.94 52.95Internal latency, nanoseconds 24 15 48 76Number of logic cells used  and  totalavailable inside the PLD3616/4160(86%)1422/2560(55%)7100/8320(85%)11383/16640(68%)V. CONCLUSIONWe have proposed a design methodology forthe implementation of the fast sorting  schemes.Four schemes  “3 objects out of 18”, “4 objectsout of 8”,  “4 objects out of 24” and “4 objectsout of 36” are implemented and simulated. Theinternal sorting latency is as low as 24, 15, 48and 76  ns for the first, second, third and fourthschemes respectively. The total latency shouldalso include a delay needed for the latching ofthe sorting result in the external registers.  Allour designs are based on the 20KE family ofAltera PLD and  can be used  at the  variouslevels of  trigger systems at the CMS and  otherexperiments.VI. REFERENCES[1] The Compact Muon Solenoid. TechnicalProposal.  CERN/LHCC 94-38.   LHCC/P1. 15December 1994. Available at:http://cmsinfo.cern.ch/TP/TP.html[2] D.Acosta et al. The  Track-FindingProcessor  for  the  Level-1  Trigger  of the CMSMuon  System.  CMS  Note 1999/060.December 8,  1999.  Available:ftp://cmsdoc.cern.ch/documents/99/note99_060.pdf[3] G.De Robertis, A.Ranieri, I.M.Kudla,G.Wrochna. The Sorting Processor Project. CMSTN/95-028.      6 March, 1995. Available at:http://cmsdoc.cern.ch/tn/95/tn95_028.pdf[4]http://cmsdoc.cern.ch/~marcodv/tridas_990519.pdf[5] Altera Device Data Book 1999. APEX 20KProgrammable Logic Device Family.[6] Xilinx Programmable Logic Data Book 2000.

Implementation of the sorting schemes in a programmable logic

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