Exploitation of Digital Filters to Advance the Single-Phase T/4 Delay PLL System

With the development of digital signal processing technologies, control and monitoring of power electronics conversion systems have been evolving to become fully digital. As the basic element in the design and analysis phases of digital controllers or filters, a number of unit delays (z-1) have been employed, e.g., in a cascaded structure. Practically, the number of unit delays is designed as an integer, which is related to the sampling frequency as well as the ac signal fundamental frequency (e.g., 50 Hz). More common, the sampling frequency is fixed during operation for simplicity and design. Hence, any disturbance in the ac signal will violate this design rule and it can become a major challenge for digital controllers. To deal with the above issue, this paper first exploits a virtual unit delay (zv-1) to emulate the variable sampling behavior in practical digital signal processors with a fixed sampling rate. This exploitation is demonstrated on a T/4 Delay Phase Locked Loop (PLL) system for a single-phase grid-connected inverter. The T/4 Delay PLL requires to cascade 50 unit delays when implemented (for a 50-Hz system with 10 kHz sampling frequency). Furthermore, digital frequency adaptive comb filters are adopted to enhance the performance of the T/4 Delay PLL when the grid suffers from harmonics. Experimental results have confirmed the effectiveness of the digital filters for advanced control systems

Analysis and mitigation of dead time harmonics in the single-phase full-bridge PWM converters with repetitive controllers

In order to prevent the power switching devices (e.g., the Insulated-Gate-Bipolar-Transistor, IGBT) from shoot through in voltage source converters during a switching period, the dead time is added either in the hardware driver circuits of the IGBTs or implemented in software in Pulse-Width Modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as "dead time harmonics" hereafter) have to be compensated in order to achieve a satisfactory current quality as required by standards. In this paper, the emission mechanism of dead time harmonics in single-phase PWM inverters is thus presented considering the modulation schemes in details. More importantly, a repetitive controller has been adopted to eliminate the dead time effect in single-phase grid-connected PWM converters. The repetitive controller has been plugged into a proportional resonant-based fundamental current controller so as to mitigate the dead time harmonics and also maintain the control of the fundamental frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm that the repetitive controller can effectively compensate the dead time harmonics and other low-order distortions, and also it is a simple method without hardware modifications