Estudi històric-constructiu i de lesions de la masia el Castell de Pujol , municipi de Coll de Nargó

El present projecte tracte de l’estudi, històric, gràfic i de lesions de la masia el Pujol, a Coll de Nargó, municipi de la comarca de l’ Alt Urgell, Aquest edifici està compost per planta baixa més plantes pis, i era una gran explotació agrícola i ramadera en els seus temps d’esplendor. L’objectiu del present projecte es realitzar un estudi de la masia partint de la història de la mateixa, analitzant el sistema constructiu i avaluant els danys i lesions que pateix la construcció. Aquest treball final de carrera està format per una sèrie d’estudis i documentació gràfica que es cita a continuació. Dades i situació de l’edifici. Es realitza una introducció de l’edifici indican la seva situació i entorn dins la finca que ocupa, així com una breu descripció de la masia i del municipi. Estudi històric: Aquest apartat comença amb la història del municipi i la comarca, per seguir amb la història dels castells a Catalunya i del castell de Pujol, i per concloure aquet apartat la història de les masies al Pirineu Català i la pròpia història del Pujol. Estudi constructiu: descriurem la masia amb profunditat, analitzant la funcionalitat de la mateixa, les superfícies construïdes i els elements estructurals que la formen. A la segona d’aquest capítol s’analitzen els sistemes estructurals i les solucions constructives adoptades per entendre el funcionament del conjunt. Estudi de lesions: es descriuen les lesions que afecten a l’edificació indicant en cada cas l’origen de la mateixa. Aquestes es classifiquen segons la seva localització poden ser, interiors o exteriors, i depenent de l’element ha que afectin, sigui paraments verticals, horitzontals o estructura. Documentació gràfica: S’ha realitzat un aixecament gràfic de l’edifici en el seu estat actual. En els plànols s’indica el sistema constructiu existent i les dimensions de la masia, així com els materials d’acabat i les lesions presents a l’actualitat, entre altres coses. Estudi de materials: per tal d’entendre una mica mes l’edifici he realitzat el present estudi de materials, calcificant-los segons la seva ubicació i funció. Annex I: per complementar l’estudi de lesions he creat unes fitxes tècniques de lesions, a les quals es tracta amb major detall cada lesió

Modelling Contention in Multicore Hardware Resources during Early Design Stages of Real-Time Systems

This thesis presents a modelling approach for the timing behavior of real-time embedded systems in early design phases. The model focuses on multicore processors and it predicts the contention tasks suffer in the access to multicore on-chip shared resources

Resilient random modulo cache memories for probabilistically-analyzable real-time systems

Fault tolerance has often been assessed separately in safety-related real-time systems, which may lead to inefficient solutions. Recently, Measurement-Based Probabilistic Timing Analysis (MBPTA) has been proposed to estimate Worst-Case Execution Time (WCET) on high performance hardware. The intrinsic probabilistic nature of MBPTA-commpliant hardware matches perfectly with the random nature of hardware faults. Joint WCET analysis and reliability assessment has been done so far for some MBPTA-compliant designs, but not for the most promising cache design: random modulo. In this paper we perform, for the first time, an assessment of the aging-robustness of random modulo and propose new implementations preserving the key properties of random modulo, a.k.a. low critical path impact, low miss rates and MBPTA compliance, while enhancing reliability in front of aging by achieving a better – yet random – activity distribution across cache sets.Peer ReviewedPostprint (author's final draft

Improving early design stage timing modeling in multicore based real-time systems

This paper presents a modelling approach for the timing behavior of real-time embedded systems (RTES) in early design phases. The model focuses on multicore processors - accepted as the next computing platform for RTES - and in particular it predicts the contention tasks suffer in the access to multicore on-chip shared resources. The model presents the key properties of not requiring the application's source code or binary and having high-accuracy and low overhead. The former is of paramount importance in those common scenarios in which several software suppliers work in parallel implementing different applications for a system integrator, subject to different intellectual property (IP) constraints. Our model helps reducing the risk of exceeding the assigned budgets for each application in late design stages and its associated costs.This work has received funding from the European Space Agency under Project Reference AO=17722=13=NL=LvH, and has also been supported by the Spanish Ministry of Science and Innovation grant TIN2015-65316-P. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.Peer ReviewedPostprint (author's final draft

Modelling bus contention during system early design stages

Reliably upperbounding contention in multicore shared resources is of prominent importance in the early design phases of critical real-time systems to properly allocate time budgets to applications. However, during early stages applications are not yet consolidated and IP constraints may prevent sharing them across providers, challenging the estimation of contention bounds. In this paper, we propose a model to estimate the increase in applications' execution time due to on-chip bus sharing when they simultaneously execute in a multicore. The model works with information derived from the execution of each application in isolation, hence, without the need to actually run applications simultaneously. The model improves inaccuracy with respect to the existing model, and tends to over-estimate. The latter, is very important to prevent that, during late design stages, applications miss their deadline when consolidated into the same multicore, causing costly system redesign.This work has been supported by the Spanish Ministry of Science and Innovation grant TIN2015-65316-P. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. Carles Hernández is jointly funded by the Spanish Ministry of Economy and Competitiveness and FEDER funds through grant TIN2014-60404-JIN.Peer ReviewedPostprint (author's final draft

On the suitability of time-randomized processors for secure and reliable high-performance computing

Time-randomized processor (TRP) architectures have been shown as one of the most promising approaches to deal with the overwhelming complexity of the timing analysis of high complex processor architectures for safety-related real-time systems. With TRPs the timing analysis step mainly relies on collecting measurements of the task under analysis rather than on complex timing models of the processor. Additionally, randomization techniques applied in TRPs provide increased reliability and security features. In this thesis, we elaborate on the reliability and security properties of TRPs and the suitability of extending this processor architecture design paradigm to the high-performance computing domain

Concert recording 2018-03-02

[Track 1]. Quartet in A major, TWV 43:A1. Soave ; Allegro ; Andante ; Vivace / Georg Phillip Telemann -- [Track 2]. Du bist verflucht, o Shreckensstimmel, TWV 1:385. Aria: Du bist verflucht o Shreckensstimme ; Recitative: So ist\u27s: Seitdem bei Edens Baum des Baum des ersten Menschen erste Sunde ; Aria: Frohlocket, ihr seligen Kinder der Freien! / Telemann -- [Track 3]. Seele, lernce dich erkennen, TWV 1:1258. Aria: Seele, lerne dich erkennen! ; Recitative: Ein Vogelchen, dem noch die Glieder ; Aria: So will ich dich mit Freuden kussen / Telemann -- [Track 4]. Sonatae unarum fidium: Sonata no. 4 in D major. Ciaccona ; Variatio ; Sarabande ; Gigue ; Adagio e recitativo ; Allegro / Johann Heinrich Schmelzer -- [Track 5]. Auf ehernen Mauern, TWV 1:96. Aria; Auf ehernen Mauern, auf marmornen Grunden ; Recitative: So lange noch der Unbestand den Schuchternen ; Aria: Ja, ja, wiederholt nur eure Tucke? / Telemann -- [Track 6]. Nouveaux Quatuors: Quartet no. 6 in E minor, TWV 43:34. Prelude; tres vite ; Gay ; Vite ; Gracieusement ; Distrait ; Modere / Telemann

Cache side-channel attacks and time-predictability in high-performance critical real-time systems

Embedded computers control an increasing number of systems directly interacting with humans, while also manage more and more personal or sensitive information. As a result, both safety and security are becoming ubiquitous requirements in embedded computers, and automotive is not an exception to that. In this paper we analyze time-predictability (as an example of safety concern) and side-channel attacks (as an example of security issue) in cache memories. While injecting randomization in cache timing-behavior addresses each of those concerns separately, we show that randomization solutions for time-predictability do not protect against side-channel attacks and vice-versa. We then propose a randomization solution to achieve both safety and security goals.This work has been partially funded by the Spanish Ministry of Science and Innovation under grant TIN2015-65316-P. Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal fellowship number RYC-2013-14717. Authors want to thank Boris Kpf for his technical comments in early versions of this work.Peer ReviewedPostprint (published version

Worst-case energy consumption: A new challenge for battery-powered critical devices

The number of devices connected to the IoT is on the rise, reaching hundreds of billions in the next years. Many devices will implement some type of critical functionality, for instance in the medical market. Energy awareness is mandatory in the design of IoT devices because of their huge impact on worldwide energy consumption and the fact that many of them are battery powered. Critical IoT devices further require addressing new energy-related challenges. On the one hand, factoring in the impact of energy-solutions on device's performance, providing evidence of adherence to domain-specific safety standards. On the other hand, deriving safe worst-case energy consumption (WCEC) estimates is a fundamental building block to ensure the system can continuously operate under a pre-established set of power/energy caps, safely delivering its critical functionality. We analyze for the first time the impact that different hardware physical parameters have on both model-based and measurement-based WCEC modeling, for which we also show the main challenges they face compared to chip manufacturers' current practice for energy modeling and validation. Under the set of constraints that emanate from how certain physical parameters can be actually modeled, we show that measurement-based WCEC is a promising way forward for WCEC estimation.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015- 65316-P and the HiPEAC Network of Excellence. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. Carles Hernndez is jointly funded by the MINECO and FEDER funds through grant TIN2014-60404-JIN.Peer ReviewedPostprint (author's final draft

Modeling the impact of process variations in worst-case energy consumption estimation

The advent of autonomous power-limited systems poses a new challenge for system verification. Powerful processors needed to enable autonomous operation, are typically power-hungry, jeopardizing battery duration. Therefore, guaranteeing a given battery duration requires worst-case energy consumption (WCEC) estimation for tasks running on those systems. Unfortunately, processor energy and power can suffer significant variation across different units due to process variation (PV), i.e. variability in the electrical properties of transistors and wires due to imperfect manufacturing, which challenges existing WCEC estimation methods for applications. In this paper, we propose a statistical modeling approach to capture PV impact on applications energy and a methodology to compute their WCEC capturing PV, as required to deploy portable critical devices.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P and the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No. 772773). MINECO partially supported Jaume Abella under Ramon y Cajal fellowship RYC-2013-14717.Peer ReviewedPostprint (author's final draft