Effects of Applied Loads, Effective Contact Area and Surface Roughness on the Dicing Yield of 3D Cu Bonded Interconnects

Bonded copper interconnects were created using thermo-compression bonding and the dicing yield was used as an indication of the bond quality. SEM images indicated that the Cu was plastically deformed. Our experimental and modeling results indicate that the effective contact area is directly proportional to the applied load. Furthermore, for first time, results have been obtained that indicate that the dicing yield is proportional to the measured bond strength, and the bond strength is proportional to the effective contact area. It is also shown that films with rougher surfaces (and corresponding lower effective bonding areas) have lower bond strengths and dicing yields. A quantitative model for the relationship between measured surface roughness and the corresponding dicing yield has been developed. An appropriate surface-roughness data acquisition methodology has also been developed. The maximum possible applied load and the minimum possible surface roughness are required to obtain the maximum effective contact area, and hence to achieve optimum yields (both mechanically and electrically).Singapore-MIT Alliance (SMA

Reliability of Multi-Terminal Copper Dual-Damascene Interconnect Trees

Electromigration tests on different Cu dual-damascene interconnect tree structures consisting of various numbers of straight via-to-via lines connected at the common middle terminal have been carried out. Like Al-based interconnects, the reliability of a segment in a Cu-based interconnect tree strongly depends on the stress conditions of connected segments. The analytic model based on a nodal analysis developed for Al trees gives a conservative estimate of the lifetime of Cu-based interconnect trees. However, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are attributed to the variations in the architectural schemes of the two metallization systems. The absence of a conducting electromigration-resistant overlayer in Cu technology and the low critical stress for void nucleation at the Cu/inter-level diffusion barrier (i.e. Si₃N₄) interface leads to different failure modes between Cu and Al interconnects. As a result, the most highly stressed segment in a Cu-based interconnect tree is not always the least reliable. Moreover, the possibility of liner rupture at stressed dual-damascene vias leads to significant differences in tree reliabilities in Cu compared to Al. While an interconnect tree can be treated as a fundamental unit whose reliability is independent of that of other units in Al-based interconnect architectures, interconnect trees can not be treated as fundamental units for circuit-level reliability analyses for Cu-based interconnects.Singapore-MIT Alliance (SMA

Beyond R&D: What Design Adds to a Modern Research University

The government of Singapore is launching a new university, the Singapore University of Technology and Design (SUTD), that is scheduled to take in its first freshman class in April, 2012. SUTD, in collaboration with MIT and Zhejiang University, is striving to establish a 21st century innovation paradigm that recognizes the synergy between innovation and design. Many aspects of such an exciting development are of interest to engineering educators and particularly to design educators and two are covered in this paper. One challenge addressed in this paper is the possibility for conflicting agendas between design‐centric education and the goal of becoming a leading research‐intensive university. An overview of research intended to address this conflict –that of the International Design Center that is jointly part of MIT and SUTD‐ is given. It is argued that, rather than conflicting, design‐centric education and research‐intensity are synergistic for a 21st century university. The second challenge discussed in some depth is the setting of “culture” for the new institution that encourages bold attempts to improve the world through technical innovation (“innovation culture”) with breadth in national cultures (“global culture”) bridging from Western to Asian perspectives. Relative to the latter item, a central feature are the “Eastern Cultural” curriculum items being developed by a second SUTD partner university ‐ Zhejiang University (Hangzhou, China). The breadth of national cultures and a wide academic disciplinary base as part of the education process are postulated to be enablers for developing a strong 21st century innovation‐leadership‐culture for the modern research university

Thermal reversible breakdown and resistivityswitching in hafnium dioxide

HfO2 nanostructures are currently considered to be very promising for different applications including gate oxides in Si transistors and emerging nonvolatile memory cells such as resistive random access memory (RRAM). For RRAM development a clear understanding of switching mechanisms from a HRS to a LRS is demanding. Several models were proposed to explain the switching effect [1-3], however, they did not cover comprehensively experimental observations. It is experimentally shown by means of high resolution transmission electron microscopy that formation of CFs with diameters of 30-50 nm in HfO2 occurred by an electrical pretreatment [2]. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/2055

Workfunction Tuning of n-Channel MOSFETs Using Interfacial Yttrium Layer in Fully Silicided Nickel Gate

Continual scaling of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-45 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided Ni metal gate (FUSI) has been proven to be a promising solution. Ni FUSI metal gate can significantly reduce gate-line sheet resistance, eliminate boron penetration to channels and has good process compatibility with high-k gate dielectric. But Ni FUSI has a mid-gap workfunction which is not suitable for high-performance CMOS applications where the band-edge workfunction is required. In this paper, we propose to tune the nickel (Ni) fully silicided metal gate (FUSI) workfunction via an yttrium/Si/Ni gate stack structure. The workfunction of such structure indicates that the Y interlayer can effectively tune the Ni FUSI workfunction from the mid gap to the conduction band edge of silicon by controlling the interlayer thickness. The gate stack workfunction starts to saturate to the pure yttrium value when the yttrium interlayer is >1.6 nm. This indicates the chemical potential of the material adjacent to gate electrode/gate insulator plays an important role in the determination of the workfunction.Singapore-MIT Alliance (SMA

Mortality Dependence of Cu Dual Damascene Interconnects on Adjacent Segments

Electromigration experiments have been carried out on straight interconnects that have single vias at each end, and are divided into two segments by a via in the center ("dotted-I" structures). For dotted-i structures in the second metal layer (M2) and with 25µm-long segments length, failures occurred even when the product of the current density and segment length (jL) was as low as 1250A/cm, even though via terminated 25µm-long lines are "immortal" when (jL)cr < 1500 A/cm. Moreover, we found the mortalities of the dotted-I segments to be dependent on the current density and current direction in the adjacent segment. These result suggest that there is not a definite value of jL product that defines true immortality in individual segments that are part of an interconnect tree, and that the critical value of jL for Cu dual damascene segments is dependent on the magnitude and direction of current flow in adjacent segments. Therefore, (jL)cr values determined in two-terminal via-terminated lines cannot be directly applied to interconnects with branched segments, but rather the magnitude as well as the direction of the current flow in the adjoining segments must be taken into consideration in determining the immortality of interconnect segments.Singapore-MIT Alliance (SMA

Effects of Platinum on NiPtSiGe/n-SiGe and NiPtSi/n-Si Schottky Contacts

Solid phase reaction of NiPt/Si and NiPt/SiGe is one of the key issues for silicide (germanosilicide) technology. Especially, the NiPtSiGe, in which four elements are involved, is a very complex system. As a result, a detailed study is necessary for the interfacial reaction between NiPt alloy film and SiGe substrate. Besides using traditional material characterization techniques, characterization of Schottky diode is a good measure to detect the interface imperfections or defects, which are not easy to be found on large area blanket samples. The I-V characteristics of 10nm Ni(Pt=0, 5, 10 at.%) germanosilicides/n-Si₀/₇Ge₀.₃ and silicides/n-Si contact annealed at 400 and 500°C were studied. For Schottky contact on n-Si, with the addition of Pt in the Ni(Pt) alloy, the Schottky barrier height (SBH) increases greatly. With the inclusion of a 10% Pt, SBH increases ~0.13 eV. However, for the Schottky contacts on SiGe, with the addition of 10% Pt, the increase of SBH is only ~0.04eV. This is explained by pinning of the Fermi level. The forward I-V characteristics of 10nm Ni(Pt=0, 5, 10 at.%)SiGe/SiGe contacts annealed at 400°C were investigated in the temperature range from 93 to 300K. At higher temperature (>253K) and larger bias at low temperature (<253K), the I-V curves can be well explained by a thermionic emission model. At lower temperature, excess currents at lower forward bias region occur, which can be explained by recombination/generation or patches due to inhomogenity of SBH with pinch-off model or a combination of the above mechanisms.Singapore-MIT Alliance (SMA

Effect of Oxygen on Ni-Silicided FUSI Metal Gate

Continual evolution of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-65 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided metal gate (FUSI) has been proven to be a promising solution. FUSI metal gate can significantly reduce gate-line sheet resistance, eliminate boron penetration to channels and has good process compatibility with high-k gate dielectric. In this paper, the effect of oxygen introduced by the process of conventional furnace annealing in FUSI metal gate is investigated. A 120 nm amorphous Si layer was sputtered on dielectric oxides of various thicknesses grown using a standard oxidation process. Raman spectra showed that the 120 nm thick pre-sputtered amorphous Si recrystallized after annealing in a conventional furnace at 900°C. Secondary ion mass spectrometry (SIMS) revealed that the annealed Si film contained traces of oxygen which were incorporated into the film during the furnace annealing process. It is suspected that the oxygen was originated from a few ppm of impurities present in the high-purity annealing gas (N2). When a 100 nm of Ni was deposited using a DC sputterer on such sample and was rapid thermal annealed (RTA) at 400°C to form a fully silicide film, the transmission electron micrograph showed the existence of unreacted oxygen-rich Si layer along the interface of the NiSi/SiO2, leading to areal non-uniformity in the workfunction. It is suggested that the presence of oxygen can effectively retard the Ni diffusion into the Si film during the silicidation process such that the FUSI process is delayed, and the equivalent oxide thickness (EOT) increased as shown by capacitance-voltage (C-V) measurements. The workfunction of Ni-silicided FUSI film determined by C-V measurement on MOS structures was found to increase compared to the as-deposited amorphous Si film (the control sample).Singapore-MIT Alliance (SMA

Effect of Pt on agglomeration and Ge out-diffusion in Ni(Pt) germanosilicide

The effect of Ni and Ni(Pt) alloy with ~5 and 10 at. % Pt on the agglomeration and Ge out-diffusion in Nickel germanosilicide formed on Si&#x2080;.&#x2087;&#x2085;Ge&#x2080;.&#x2082;&#x2085;(100) has been studied. A remarkable improvement in the agglomeration behavior with increasing Pt atomic percentage is observed by sheet resistance measurements and scanning electron microscopy (SEM). In addition, x-ray diffraction (XRD) shows that only NiSiGe or Ni(Pt)SiGe phase exists from 400 to 800°C. However, Ge out-diffusion from the monogermanosilicide grains is obvious at 600°C and 700°C for Ni/SiGe and Ni(Pt)(Pt at.%~10%)/SiGe, respectively, evident by XRD and micro-Raman spectroscopy. The improved melting temperature of Ni(Pt)SiGe solution compared to that of NiSiGe is the likely reason of seeing better surface morphology and suppressing Ge out-diffusion of the germanosilicide grains observed.Singapore-MIT Alliance (SMA

Preliminary Characterisation of Low-Temperature Bonded Copper Interconnects for 3-D Integrated Circuits

Three dimensional (3-D) integrated circuits can be fabricated by bonding previously processed device layers using metal-metal bonds that also serve as layer-to-layer interconnects. Bonded copper interconnects test structures were created by thermocompression bonding and the bond toughness was measured using the four-point test. The effects of bonding temperature, physical bonding and failure mechanisms were investigated. The surface effects on copper surface due to pre-bond clean (with glacial acetic acid) were also looked into. A maximum average bond toughness of approximately 35 J/m² was obtained bonding temperature 300 C.Singapore-MIT Alliance (SMA