Continual scaling of the CMOS technology requires thinner gate dielectric to maintain high performance. However, when moving into the sub-45 nm CMOS generation, the traditional poly-Si gate approach cannot effectively reduce the gate thickness further due to the poly-depletion effect. Fully silicided Ni metal gate (FUSI) has been proven to be a promising solution. Ni FUSI metal gate can significantly reduce gate-line sheet resistance, eliminate boron penetration to channels and has good process compatibility with high-k gate dielectric. But Ni FUSI has a mid-gap workfunction which is not suitable for high-performance CMOS applications where the band-edge workfunction is required. In this paper, we propose to tune the nickel (Ni) fully silicided metal gate (FUSI) workfunction via an yttrium/Si/Ni gate stack structure. The workfunction of such structure indicates that the Y interlayer can effectively tune the Ni FUSI workfunction from the mid gap to the conduction band edge of silicon by controlling the interlayer thickness. The gate stack workfunction starts to saturate to the pure yttrium value when the yttrium interlayer is >1.6 nm. This indicates the chemical potential of the material adjacent to gate electrode/gate insulator plays an important role in the determination of the workfunction.Singapore-MIT Alliance (SMA
