On the construction of parallel computers from various bases of Boolean functions

The effects of bases of two-input boolean functions are characterised in terms of their impact on some questions in parallel computation. It is found that a certain set of bases (called the P-complete set) which are not necessarily complete in the classical sense, apparently makes the circuit value problem difficult, and renders extended Turing machines and conglomerates equal to general parallel computers. A class of problems called EP arises naturally from this study, relating to the parity of the number of solutions to a problem, in contrast to previously defined classes concerning the count of the number of solutions (#P) or the existence of solutions to a problem (NP). Tournament isomorphism is a member of EP

An improved simulation of space and reversal bounded deterministic turing machines by width and depth bounded uniform circuits

We present an improved simulation of space and reversal bounded Turing machines by width and depth bounded uniform circuits. (All resource bounds hold simultaneously.) An S(n) space, R(n) reversal bounded deterministic k-tape Turing machine can be simulated by a uniform circuit of O(R(n) log2S(n)) depth and O(S(n) k) width. Our proof is cleaner, and has slightly better resource bounds than the original proof due t

A prototype quest generator based on a structural analysis of quests from four mmorpgs

ABSTRACT An analysis of over 750 quests from four popular RPGs (Eve Online, World of Warcraft, Everquest, and Vanguard: Saga of Heroes) reveals that RPG quests appear to share a common structure. We propose a classification of RPG quests based on this structure, and describe a prototype quest generator based on that classification. Our aim is to procedurally generate quests that are complex, multi-leveled, and plausible to players of RPGs. We analyze a nontrivial quest from Everquest and one from our prototype quest generator for comparison

Formalizing Size-Optimal Sorting Networks: Extracting a Certified Proof Checker

Since the proof of the four color theorem in 1976, computer-generated proofs have become a reality in mathematics and computer science. During the last decade, we have seen formal proofs using verified proof assistants being used to verify the validity of such proofs. In this paper, we describe a formalized theory of size-optimal sorting networks. From this formalization we extract a certified checker that successfully verifies computer-generated proofs of optimality on up to 8 inputs. The checker relies on an untrusted oracle to shortcut the search for witnesses on more than 1.6 million NP-complete subproblems.Comment: IMADA-preprint-c

Non-deterministic Boolean Proof Nets

16 pagesInternational audienceWe introduce Non-deterministic Boolean proof nets to study the correspondence with Boolean circuits, a parallel model of computation. We extend the cut elimination of Non-deterministic Multiplicative Linear logic to a parallel procedure in proof nets. With the restriction of proof nets to Boolean types, we prove that the cut-elimination procedure corresponds to Non-deterministic Boolean circuit evaluation and reciprocally. We obtain implicit characterization of the complexity classes NP and NC (the efficiently parallelizable functions)

On Second-Order Monadic Monoidal and Groupoidal Quantifiers

We study logics defined in terms of second-order monadic monoidal and groupoidal quantifiers. These are generalized quantifiers defined by monoid and groupoid word-problems, equivalently, by regular and context-free languages. We give a computational classification of the expressive power of these logics over strings with varying built-in predicates. In particular, we show that ATIME(n) can be logically characterized in terms of second-order monadic monoidal quantifiers

On Uniformity and Circuit Lower Bounds

Abstract—We explore relationships between circuit complexity, the complexity of generating circuits, and algorithms for analyzing circuits. Our results can be divided into two parts: 1. Lower Bounds Against Medium-Uniform Circuits. Informally, a circuit class is “medium uniform ” if it can be generated by an algorithmic process that is somewhat complex (stronger than LOGTIME) but not infeasible. Using a new kind of indirect diagonalization argument, we prove several new unconditional lower bounds against medium uniform circuit classes, including: • For all k, P is not contained in P-uniform SIZE(n k). That is, for all k there is a language Lk ∈ P that does not have O(n k)-size circuits constructible in polynomial time. This improves Kannan’s lower bound from 1982 that NP is not in P-uniform SIZE(n k) for any fixed k

Full vs Partial Market Coverage with Minimum Quality Standards

The consequences of the adoption of quality standards on the extent of market coverage is investigated by modelling a game between regulator and low-quality firm in a vertically differentiated duopoly. The game has a unique equilibrium in the most part of the parameter range. There exists a non-negligible range where the game has no equilibrium in pure strategies. This result questions the feasibility of MQS regulation when firms endogenously determine market coverage

Experimental Aspects of Synthesis

We discuss the problem of experimentally evaluating linear-time temporal logic (LTL) synthesis tools for reactive systems. We first survey previous such work for the currently publicly available synthesis tools, and then draw conclusions by deriving useful schemes for future such evaluations. In particular, we explain why previous tools have incompatible scopes and semantics and provide a framework that reduces the impact of this problem for future experimental comparisons of such tools. Furthermore, we discuss which difficulties the complex workflows that begin to appear in modern synthesis tools induce on experimental evaluations and give answers to the question how convincing such evaluations can still be performed in such a setting.Comment: In Proceedings iWIGP 2011, arXiv:1102.374