We present an improved simulation of space and reversal bounded Turing machines by width and depth bounded uniform circuits. (All resource bounds hold simultaneously.) An S(n) space, R(n) reversal bounded deterministic k-tape Turing machine can be simulated by a uniform circuit of O(R(n) log2S(n)) depth and O(S(n) k) width. Our proof is cleaner, and has slightly better resource bounds than the original proof due t

Ian Parberry

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Information Processing Letters 24 (1987) 363-367 6 April 1987 
North-Holland 
AN IMPROVED SIMULATION OF SPACE AND REVERSAL BOUNDED DETERMINISTIC 
TURING MACHINES BY WIDTH AND DEPTH BOUNDED UNIFORM CIRCUITS 
Ian PARBERRY 
v 
Department of Computer Science, The Pennsylvania State University, University Park, PA 16802, U.S.A. 
Communicated by David Giles 
Received 12 May 1986 
Revised 4 August 1986 
We present an improved simulation of space and reversal bounded Turing machines by width and depth bounded uniform 
circuits. (All resource bounds hold simultaneously.) An S(n) space, R(n) reversal bounded deterministic k-tape Turing machine 
can be simulated by a uniform circuit of O(R(n) log2S(n)) depth and O(S(n) k) width. Our proof is cleaner, and has slightly 
better resource bounds than the original proof due to Pippenger (1979). The improvement in resource bounds comes primarily 
from the use of a shared-memory machine instead of an oblivious Turing machine, and the concept of a 'special situation'. 
Keywords: Deterministic k-tape Turing machine, shared-memory machine, uniform circuit, reversal, NC, extended parallel 
computation thesis, reduction to sorting, simultaneous resource bounds 
1. Introduction 2. Some machine models 
Pippenger [16] has demonstrated that NC (the 
class of languages recognized by polynomial size, 
polylog depth uniform circuits) is precisely the 
class of languages recognized by polynomial space, 
polylog reversal deterministic Turing machines. 
We assume the reader to be familiar with the 
terminology of that paper, and for conciseness will 
restrict ourselves mainly to those definitions which 
differ for technical reasons. Pippenger's simula- 
tion of Turing machines by circuits makes fre- 
quent use of a reduction to sorting. We obtain a 
more straightforward proof, with a slight improve- 
ment  in resource bounds, using a single reduction. 
A preliminary version of the results in this 
paper have appeared in [14], and in the author's 
Ph.D. thesis [13]. The reader requiring a more 
detailed account is directed to the latter reference. 
The remainder of this paper is divided into two 
sections, the first containing some definitions, and 
the second containing the result. 
In this section we sketch two popular parallel 
machine models. Let Z denote the set of integers 
and N denote the set of natural numbers. Let 
D, P, S, T, W, Z : N  ~ N. 
A shared-memory machine consists of an in- 
finite number of processors attached to a globally 
accessible shared memory. Each processor pos- 
sesses an infinite number of general purpose reg- 
isters, and a unique read-only processor identity 
register PID which is preset to i in the ith 
processor, i ~ N. A program for this machine 
consists of a finite list of instructions; each in- 
struction is of the form either: 
(i) read a value from the shared memory, 
(ii) write a value to the shared memory, 
(iii) perform an internal computation, 
(iv) conditional transfer of control or halt. 
The allowable internal computations usually 
consist of direct and indirect register transfers, 
and arithmetic operations. We will allow the arith- 
0020-0190/87/$3.50 © 1987, Elsevier Science Publishers B.V. (North-Holland) 363 
Volume 24, Number ~ INFORMATION PROCESSING LETTERS 6 April 1987 
metic operations of addition, subtraction and mul- 
tiplication and division by powers of two. 
More formally, a shared-memory machine is 
specified by a program 9 ~ and a processor bound 
P(n). A computation proceeds roughly as follows. 
An input of size n (where the 'size' measure de- 
pends on the problem in question) is broken up 
into n unit-size pieces, and the ith piece is en- 
coded as an integer and stored in shared memory 
location i, 0 ~< i < n. All other memory locations 
and general purpose registers are set to zero. 
Processors 0, 1 , . . . ,  P ( n ) -  1 are activated simulta- 
neously; they synchronously execute the program 
~ .  When all processors have halted, the output is 
to be found in some specified place in the shared 
memory. 
The processor bound P(n) is a measure of the 
number of processors used as a function of input 
size. The space S(n) is the maximum number of 
nonzero entries in the shared memory and reg- 
isters at any time during the computation. (Note 
that this includes the input and the processor 
identity registers, so S(n) >/n + P(n) - 1.) The 
machine is said to have word-size W(n) if every 
value placed into a register or shared memory 
location during a computation on an input of size 
n has absolute value less than 2 w(~). The time 
bound T(n) is the number of instructions executed 
before all processors have halted, again as a func- 
tion of input size. 
Variants of this model have appeared, for ex- 
ample, in [9,10,11,12,18,19,20,21,22]. We assume 
some reasonable protocol for dealing with mem- 
ory access conflicts, as in those references. The 
general consensus of opinion is that whilst the 
shared-memory model is a powerful theoretical 
tool, it is not feasibly buildable using any fore- 
seeable technology. Note that our space bound is 
slightly unusual. It is more normal to measure the 
'number  of registers or memory locations used' 
regardless of the amount of time during which 
they are active (see, for example, [1] for the case of 
a single RAM). 
A uniform circuit is an  infinite family C = 
(Co, Ca . . . .  ) of combinational circuits, one for each 
input size (see, for example, [5,6,16,17]). Without 
loss of generality we assume that the circuits are 
built using gates which realize functions drawn 
from the class B: of two-input Boolean functions. 
An input of size n is presented, in some suitably 
encoded form, to the inputs of C n. The output of 
C n is then taken as the output of C. C is said to 
have depth D(n) if the length of the longest path 
from an input to an output in Cn is at most D(n), 
for n >~ 0. It has width W(n) if Cn has width (as 
defined in [16]) W(n) and size Z(n) if Cn has Z(n) 
gates. We assume D(n) = ~ (log W(n)). 
The function f :N2)< (left, r igh t} -oN,  where 
for n >i 0 the j-input of gate i >~ n is connected to 
the output of gate f(i, n, j) (we assume that gates 
0, 1 , . . . ,  n - 1 are distinguished gates representing 
the inputs), is called the interconnection function of 
C. The function g : N 2 _.. ]32 ' where for n >~ 0 gate 
i >/n of C~ is a g(i, n)-gate, is called the gate 
function of C. We insist that the interconnection 
and gate functions be computable by a determinis- 
tic Turing machine in O(log Z(n)) space. 
2.1. Lemma. Every shared-memory machine which 
uses S(n) space, T(n) time and W(n) word-size can 
be simulated by a uniform circuit of O(T(n) log S(n)) 
depth and O(S(n)W(n)) width. 
Proof. The proof uses the common method of 
' reduction to sorting' (see, for example, [13,14,15]), 
and the sorting network of Ajtai, Koml6s and 
Szemerrdi [2,3]. [] 
3. The simulation theorem 
The extended parallel computation thesis of 
Dymond [7] (see also [8]) states that parallel time 
and hardware (on any 'reasonable' model) are 
simultaneously polynomially equivalent to rever- 
sals and space on a deterministic Turing machine. 
The justification for this is based on the seminal 
paper by Pippenger [16] which relates depth and 
size of uniform circuits to Turing machine rever- 
sals and time. Dymond prefers to use Turing 
machine space instead of time, and circuit width 
as a measure of hardware (rather than size) since 
it is a measure of the amount of hardware which 
comes into play at any given instant in time. The 
aim of this section is to provide an improved 
simulation of space and reversal bounded Turing 
364 
Volume 24, Number 6 INFORMATION PROCESSING LETTERS 6 April 1987 
machines by width and depth bounded uniform 
circuits. 
We follow the general structure of the proof 
appearing in [16]. Pippenger simulates a Turing 
machine on an oblivious Turing machine, and 
then simulates this on a uniform circuit. We will 
simulate a Turing machine on a shared-memory 
machine. We can then build a uniform circuit by 
application of Lemma 2.1. 
3.1. Theorem. An S(n) space, R(n) reversal bounded 
k-tape deterministic Turing machine can be simu- 
lated on a shared-memory machine with O(S(n)k/ 
log S(n)) processors and space, O(R(n) log S(n)) 
time, and O(log S(n)) word-size. 
Proof. Let M be a k-tape deterministic Turing 
machine which runs in S(n) space and R(n) rever- 
sals. Following [16] define a phase to be all the 
steps of M from one reversal to the next (the first 
move is counted as a reversal for this purpose), 
and a situation to be the control state and head 
positions of M. It may be assumed that all transi- 
tion rules of M which write a new value onto a 
tape cell also move the head away from that cell. 
This implies that symbols written during one phase 
cannot be read until the next. Let d(n)--- 
2I~og ~og so~)l and call a situation special if it has at 
least one head on the ( i-d(n))th cell of its tape, 
for some i ~ N .  Note that there are at most 
O(S(n)k/1og S(n)) special situations, and that at 
most O(log S(n)) steps of M can occur between 
special situations. 
The simulation proceeds roughly as follows. 
The tape contents at the start of the current phase, 
the head directions and the initial situation for the 
current phase are stored in the shared memory. 
This is easy to do at the start of the initial phase; 
the algorithm will maintain this information from 
phase to phase. We reserve one processor (and two 
shared-memory locations) for each special situa- 
tion. The aim is to have these processors confer, 
via the shared memory, and decide which special 
situations are involved in the current phase. The 
processors corresponding to these special situa- 
tions then simultaneously update the tape cell 
contents in shared memory; the final situation 
(which is detected by an attempted reversal) de- 
termines the head directions and the initial situa- 
tion for the next phase. This proceeds for a total 
of R(n) phases. 
The simulation of a phase is achieved as fol- 
lows. Processor i handles the ith special situation. 
Firstly, each processor i computes in parallel the 
special situation which follows from special situa- 
tion i, by doing a step-by-step read-only simula- 
tion of M on the tape contents in shared memory 
(by 'read-only simulation' we mean that the tape- 
contents are not updated). This value is stored 
into array element s[i] in shared memory. If an 
illegal situation occurs during this process, or a 
reversal is detected (determined by examining the 
head directions for the current phase, which are 
stored in shared memory), then s[i] is set to i. All 
processors i execute the following code synchro- 
nously in parallel. Before activation, shared array 
element active[i] is set to true iff situation i is the 
first situation in the current phase. Upon termina- 
tion, active[i] will be true iff special situation i 
occurs in the current phase. Each processor can 
determine whether its special situation is the first 
special situation to occur in the current phase by 
using a step-wise read-only simulation of M start- 
ing at the initial situation of the phase. 
for b := 1 to [log S(n)] do 
if active[i] then active[s[i]] := true 
s[i] := s[s[i]] 
Suppose that s o is the initial situation of the 
current phase, and that the subsequent situations 
in the current phase are s l , . . .  , Ss0~)-l. It can easily 
be proved by induction on m that after the ruth 
interation of the for-loop, active[sj] is true for 
0 ~< j < 2 m, active[i] is false for all other situations 
i, and 
= f sj+2" for 0 ~< j < S(n) - 2 m, 
SIs j] 
sj for  S(n)  - 2 m ~< j < S(n) .  
Those processors i with active[i] = true can then 
update the tape contents; the last special situation 
is readily available (in all entries of s), from which 
the final situation of the current phase can be 
determined. The running time is dominated by 
O(log S(n)) for each phase. This comes from: 
365 
Volume 24, Number 6 INFORMATION PROCESSING LETTERS 6 April 1987 
(1) decoding of PIDs (each of O(log S(n)) bits) 
into special situations, 
(2) determining the first special situation from 
the initial situation and the final situation from 
the last special situation by simulating at most 
O(log S(n)) steps of M, 
(3) computing the special-situation transition 
function by simulating O(log S(n)) steps of M, 
(4) computing the active array in O(log S(n)) 
steps, 
(5) updating the tape contents by simulating 
O(log S(n)) steps of M. 
Repeating this for R(n) phases gives us the 
required result. D 
3.2. Corollary. An S(n) space, R(n) reversal 
bounded deterministic k-tape Turing machine can be 
simulated by a uniform circuit of O(R(n) log2S(n)) 
depth and O(S(n) k) width. 
Proof. The proof follows from Theorem 3.1 and 
Lemma 2.1. [] 
3.3. Corollary. A T(n) time, R(n) reversal bounded 
deterministic k-tape Turing machine can be simu- 
lated by a uniform circuit of O(R(n)logeT(n)) 
depth and O(R(n)T(n)klog2T(n)) size. 
This is a small improvement over the original 
results of Pippenger [16], whose size and depth 
bounds are inferior by a factor of O(log2T(n)). 
Our improvements can be summarized as follows: 
(i) A factor of O(log T(n)) is easily removed 
from both the size and the depth by using the 
sorting network of Ajtai, Koml6s and Szemer&li 
in place of the sorting network (due to Batcher [4]) 
used by Pippenger. 
(ii) A factor of O(log T(n)) is removed from 
the depth by using shared-memory machines in- 
stead of oblivious Turing machines. 
(iii) A factor of O(log T(n)) is removed from 
the size by using 'special situations'. 
Acknowledgment 
The author wishes to thank Mike Paterson for a 
suggestion which led to the concept of a 'special 
situation'. 
366 
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367 


An improved simulation of space and reversal bounded deterministic turing machines by width and depth bounded uniform circuits

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An improved simulation of space and reversal bounded deterministic turing machines by width and depth bounded uniform circuits

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