Design and VHDL Modeling of All-Digital PLLs

International audienceIn this paper, a VHDL model of a second-order alldigital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability issues related with asynchronous operation of the digital PFD. This particular architecture of the digital PHD is required by the synchronised operation of the ADPLL network in the context of distributed clock generator. The whole ADPLL model have been validated by purely behavioral (VHDL) and mixed simulation, in which the digital PFD detector was represented by its transistorlevel model

A Design Approach for Networks of Self-Sampled All-Digital Phase-Locked Loops

International audienceThis paper addresses the problem of the stability and the performance analysis of N-nodes Cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated that under certain conditions (such as filter coefficients value) a global and a local synchronization can be obtained. Our approach to find the optimal conditions consists in analyzing an corresponding linear average system of the Cartesian network rather than constructing a piecewise-linear system which is extremely difficult to analysis. The constructed corresponding system takes into account the non-linearity of the network and especially the self-sampling property. It is then analyzed by linear performance criteria such as modulus margin to guarantee a robust stability of the Cartesian network. The reliability of our approach is proved by transient simulations in networks of different sizes

FPGA implementation of reconfigurable ADPLL network for distributed clock generation

International audienceThis paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations

Distributed clock generator for synchronous SoC using ADPLL network

International audienceThis paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs

Horlogerie distribuée pour les SoCs synchrones

This dissertation addresses the problem of global synchronization of complex SoC in the context of deeply submicron CMOS technologies. Nowadays, to circumvent the difficulties associated with conventional clock distribution techniques (e.g. tree, mesh) in synchronous systems, the designers wishing to go on with the Globally Synchronous paradigm are turning toward clocking techniques breaking away from conventional approaches (e.g. distributed oscillators, stationary waves, coupled oscillators, programmable delays). This study is situated on this research axis. In this research we studied and elaborated a global distributed clocking system for a highly reliable synchronous circuit. This clocking scheme is based on a network of oscillators coupled in phase. Inside each synchronous clocking domain, there is one oscillator that generates the local clock. To synchronize the oscillators (i.e. domains), each one of them is controlled by an All-Digital Phase Locked Loop (ADPLL), realizing a phase coupling between the oscillators of neighboring zones. During this research we have developed the specifications and selected an architecture of the network. A theoretical model of the system has been established in a collaboration with CEA-LETI and Supélec laboratories in the framework of ANR HODISS project. We have analyzed the behavior of the system in simulations on different abstraction levels, investigated the stability conditions of its synchronous operation. An All-Digital Phase Locked Loop (ADPLL) has been proposed for the role of an elementary node of distributed clocking network. The use of ADPLL permits to circumvent difficulties of implementation, which are usually associated with analog PLL. We have designed the main blocks of the ADPLL: a Digitally-Controlled Oscillator (DCO), a Phase-Frequency Detector (PFD) and an error processing block. A cell-based design technique has been adapted for the design of DCO layout. This technique significantly reduced the complexity of the oscillator's implementation. The remaining blocks have been designed in a common digital design flow. In order to reduce the risks associated with silicon implementation, the system has been validated in a FPGA prototyping platform. The results of the measurements showed that clocking network behaves as predicted by the theory and simulations. Two prototype circuits have been designed, implemented and tested in a 65 nm STMicroelectronics CMOS technology. The first one is a proof of concept of a designed highly linear and monotonous DCO. The measured parameters of oscillator showed the compliance with specifications. The measured performance demonstrated the <15 ps rms jitter, while consuming 6.2 mW/GHz with 1.1 V supply voltage. The tuning range of the oscillator is 999-2480 MHz under 10 bit resolution. The second chip is a 4x4 node clocking network which consists of 16 distributed ADPLLs. Each of them employs a designed earlier DCO, PFD and error processing block. The experiments showed that proposed technique of distributed clock generation is feasible in a real CMOS chip environment. The measured performance demonstrated the timing error between neighbor oscillators less than 60 ps, while power consumption is 98.47 mW/GHz.Cette thèse aborde le problème de génération d'horloge globale dans les SoCs complexes dans le contexte des technologies CMOS profondément submicroniques. Actuellement, afin de contourner les difficultés liées aux techniques classiques de distribution d'horloge (p.ex. arbre, grille) dans les systèmes synchrones, les concepteurs qui désirent de se rendre sur le paradigme Synchronisation Globale se tournent vers les techniques de synchronisation rompant avec les approches classiques (par exemple oscillateurs distribués, les ondes stationnaires , oscillateurs couplés, les retards programmables). Cette étude s'inscrit dans ce courant. Dans ce travail, nous avons étudié et mis au point un système de génération d'horloge sur puce destiné à un SoC synchrone de haute fiabilité. Cette architecture est basée sur un réseau d'oscillateurs couplés en phase et en fréquence à l'aide d'un réseaux de boucles à verrouillage de phase tout numériques (ADPLLs). Pendant cette recherche nous avons mis au point les spécifications et choisi une architecture de réseau. Un modèle théorique du système a été mis en place en collaboration avec CEA-LETI et Supélec dans le cadre du projet ANR HODISS. Nous avons analysé le comportement du système dans les simulations sur différents niveaux d'abstraction, en enquêtant des conditions de stabilité de son fonctionnement synchrone. L'ADPLL a été proposé comme un nœud élémentaire du réseau de synchronisation distribuée. L'utilisation d'ADPLL permet de contourner les difficultés d'implémentation, qui sont généralement associées à PLL analogique. Nous avons conçu les blocs principaux de l'ADPLL: un oscillateur à commande numérique (Digitally-Controlled Oscillator, DCO), un détecteur de phase/fréquence (PFD) et un bloc de traitement d'erreur. Une technique de conception basée sur les cellules a été adapté pour le développement d'oscillateur. Cette technique réduit considérablement la complexité de l'implémentation de l'oscillateur. Les autres blocs ont été conçus en utilisant un flot de conception numérique commun. Afin de réduire les risques associés à l'implémentation de silicium, le système a été validé dans une plate-forme de prototypage FPGA. Les résultats des mesures ont montré que la synchronisation de réseau se comporte comme prédit par la théorie et ainsi que les simulations. Deux circuits de prototypage ont été conçus, mis en œuvre et testés dans une technologie CMOS 65 nm de STMicroelectronics. La première puce est une preuve de concept d'un DCO conçu très linéaire et monotone. Les paramètres mesurés de l'oscillateur sont conformes aux spécifications. La performance mesurée a démontré une gigue de moins de 15 ps rms, en consommant 6.2 mW/GHz @ 1.1 V. La plage de réglage de l'oscillateur est 999-2480 MHz avec une résolution de 10 bits. La deuxième puce est un réseau d'horloge avec 4x4 nœuds qui se compose de 16 ADPLLs distribués. Chacun d'entre eux utilise les blocs conçu précédemment: DCO, PFD et bloc de traitement d'erreur. Les expérimentes ont montré que la technique proposée de génération d'horloge distribuée est réalisable sur une puce réelle CMOS. La performance mesurée démontre l'erreur de synchronisation entre les oscillateurs voisins moins de 60 ps, alors que la consommation d'énergie est 98.47 mW/GHz

Horlogerie distribuée pour les SoCs synchrones

This dissertation addresses the problem of global synchronization of complex SoC in the context of submicron CMOS technologies.Nowadays, to circumvent the difficulties associated with conventional clock distribution techniques in synchronous systems, the designers wishing to go on with the Globally Synchronous paradigm are turning toward clocking techniques breaking away from conventional approaches.In this research we studied and elaborated a global distributed clocking system for a highly reliable synchronous circuit. This clocking scheme is based on a network of oscillators coupled in phase. To synchronize the oscillators (i.e. domains), each one of them is controlled by an All-Digital Phase Locked Loop (ADPLL), realizing a phase coupling between the oscillators of neighboring zones. The use of ADPLL permits to circumvent difficulties of implementation, which are usually associated with analog PLL.Two prototype circuits have been designed, implemented and tested in a 65 nm STMicroelectronics CMOS technology. The first one is a proof of concept of a designed highly linear and monotonic DCO. The measured performance demonstrated the 15 ps rms jitter, while consuming 6.2 mW/GHz with 1.1 V supply voltage. The tuning range of the oscillator is 1-2.5 GHz under 10 bit resolution.The second chip is a 4x4 node clocking network which consists of 16 distributed ADPLLs. The experiments showed that proposed technique of distributed clock generation is feasible in a real CMOS chip environment. The measured performance demonstrated the timing error between neighbor oscillators less than 60 ps, while power consumption is 98.47 mW/GHz.Cette thèse aborde le problème de génération d'horloge globale dans les SoCs complexes dans les technologies CMOS submicroniques.Actuellement, afin de contourner les difficultés liées aux techniques classiques de distribution d'horloge dans les systèmes synchrones, les concepteurs se tournent vers les techniques de synchronisation rompant avec les approches classiques (par exemple oscillateurs distribués, les ondes stationnaires, oscillateurs couplés, les retards programmables).Dans ce travail, nous avons étudié et mis au point un système de génération d'horloge sur puce destiné à un SoC synchrone de haute fiabilité. Cette architecture est basée sur un réseau d'oscillateurs couplés en phase et en fréquence à l'aide d'un réseau de boucles à verrouillage de phase tout numériques (ADPLLs). La principale innovation de ce travail se trouve dans le fait que cette architecture est entièrement réalisée à l'aide des circuits numériques. L'utilisation d'ADPLL permet de contourner les difficultés d'implémentation, qui sont généralement associées à PLL analogique.Deux circuits de prototypage ont été conçus, mis en oeuvre et testés dans une technologie CMOS 65 nm de STM. La première puce est une preuve de concept d'un DCO hautement linéaire, à plage des fréquences de 1-2.5 GHz avec une résolution de 10 bits.La deuxième puce est un réseau 4x4 de génération d'horloge composé de 16 ADPLLs distribués. Les tests ont montré que la technique proposée de génération d'horloge distribuée est réalisable sur une puce réelle CMOS. La performance mesurée démontre l'erreur de synchronisation entre les oscillateurs voisins moins de 60 ps, alors que la consommation d'énergie est 98.47 mW/GHz.PARIS-BIUSJ-Mathématiques rech (751052111) / SudocSudocFranceF

Radiative Effects on MRAM-Based Non-Volatile Elementary Structures

International audienceRadiation robust circuit design for harsh environments like space is a big challenge for today engineers and researchers. As circuits become more and more complex and CMOS processes get denser and smaller, their immunity towards particle strikes decreases drastically. This work has for objective to improve the System on Chip (SoC) robustness against particle attacks targeting very advanced processes. This should be possible combining three already proven robust design techniques: Asynchronous communication, Silicon on Insulator (SOI) technologies and Spintronics. The combination of these three techniques should give some fundamentally new architecture with higher performances than what is available today in terms of robustness but also in terms of speed, consumption and surface

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs

International audienceThis paper presents a Cartesian network of CMOS oscillators distributed on a chip and synchronized by a network of all-digital PLLs in phase and in frequency. Such a network may be used for generation of a global clock in large digital systems on chip. The originality of the work is in the use of a solution essentially based on digital circuits. This offers many opportunities for implementation of different algorithms of synchronization, depending on the application context and operational conditions. The synchronization algorithm is based on a PI control applied to the phase error measured between neighbors. In this way, the global synchronization is achieved through a local control: such an architecture is compatible with the concept of networks on chip, a largely spread concept in the worlds of VLSI circuits. The paper presents two prototypes demonstrating the feasibility and reliability of the proposed solution for synchronization

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

This brief presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700–840 MHz at VDD=1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 μW /MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the start-up frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.Enterprise IrelandFrench National Agency of Research (ANR

Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks

International audienceIn this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a time-to-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design. In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement