Electrical characterization of top-gated molybdenum disulfide field-effect-transistors with high-k dielectrics

High quality HfO2 and Al2O3 substrates are fabricated in order to study their impact on top-gate MoS2 transistors. Compared with top-gate MoS2 FETs on a SiO2 substrate, the field effect mobility decreased for devices on HfO2 substrates but substantially increased for devices on Al2O3 substrates, possibly due to substrate surface roughness. A forming gas anneal is found to enhance device performance due to a reduction in charge trap density of the high-k substrates. The major improvements in device performance are ascribed to the forming gas anneal. Top-gate devices built upon Al2O3 substrates exhibit a near-ideal subthreshold swing (SS) of ~ 69 mV/dec and a ~ 10 × increase in field effect mobility, indicating a positive influence on top-gate device performance even without any backside bias

Relatively low-temperature processing and its impact on device performance and reliability

Non-silicon, large-area/flexible electronics for the internet of things (IoT) has acquired substantial attention in recent years. Key electron devices to enable this technology include metal-oxide-semiconductor field effect transistors (MOSFETs), where ultra-thin and/or low-dimensional (i.e., 2D to a few layers) semiconductor materials may be required, like those found in thin-film transistors (TFTs) and transition metal dichalcogenide (TMD) FETs [1,2]. Whether TFT or TMDFET, a relatively low-temperature process commensurate with large-area/flex applications to enable large (i.e., greater than 300 mm) and/or flexible substrate fabrication is required. Furthermore, TMD materials may be implemented as the channel semiconductor to function as an ultra-thin body to mitigate short channel effects and extend further scaling as the future progresses in CMOS scaling. In addition, the gate dielectric insulator is another vital component of any MOSFET that requires investigation as part of the MOS stack in these types of transistors. Lastly, semiconductor materials mentioned herein do not have a universally accepted way to introduce dopants to form sources and drains. Thus, metal-semiconductor contacts are employed where the interface region of the contact plays a critical role in determining the conductivity/resistivity of the contact. Moreover, how the metal-semiconductor interface are formed also impacts the quality of the contact. Therefore, exploration of low-temperature processing, interfaces, and their impact on device performance and reliability will be critical to eventual implementation in future technologies. To ascertain the impact of low-temperature fabrication and critical interfaces, several process approaches and electrical characterization methods were employed [1-6]. In one case, for a TMD FET contact study, an oxygen plasma exposure in the contact region on MoS2 (a TMD material) is done prior to titanium deposition. The results demonstrate that contaminants and photoresist residue that still reside after development can noticeably impact electrical performance (Fig. 1). The O2 plasma removes the residue present at the surface of MoS2 without the use of a high temperature anneal, and subsequently improves the device performance significantly (Fig. 1) [1]. In another case, for a MOS-based TFT study, an investigation of low-temperature (\u3e 115°C) deposited zinc-based semiconductors was executed (Fig. 2). For ZnO and IGZO, saturation mobilities of 14.4 and 8.4 cm2/V-s, along with threshold voltages of 2.2 V and 2.0 V were obtained, respectively, demonstrating robust devices that also have an on/off ratio \u3e 108, with IOFF lower than 10-12 A. Furthermore, a hot carrier stress methodology demonstrated threshold voltage (VTH) shifts of 0.4 V and 1.8 V for ZnO and IGZO, respectively, after stress (Fig. 2) [2]. Continued research is required to ascertain the electrically active defects responsible for the VTH shift. Please click Additional Files below to see the full abstract

Probing interface defects in top-gated MoS2 transistors with impedance spectroscopy

The electronic properties of the HfO2/MoS2 interface were investigated using multifrequency capacitance–voltage (C–V) and current–voltage characterization of top-gated MoS2 metal–oxide–semiconductor field effect transistors (MOSFETs). The analysis was performed on few layer (5–10) MoS2 MOSFETs fabricated using photolithographic patterning with 13 and 8 nm HfO2 gate oxide layers formed by atomic layer deposition after in-situ UV-O3 surface functionalization. The impedance response of the HfO2/MoS2 gate stack indicates the existence of specific defects at the interface, which exhibited either a frequency-dependent distortion similar to conventional Si MOSFETs with unpassivated silicon dangling bonds or a frequency dispersion over the entire voltage range corresponding to depletion of the HfO2/MoS2 surface, consistent with interface traps distributed over a range of energy levels. The interface defects density (Dit) was extracted from the C–V responses by the high–low frequency and the multiple-frequency extraction methods, where a Dit peak value of 1.2 × 1013 cm–2 eV–1 was extracted for a device (7-layer MoS2 and 13 nm HfO2) exhibiting a behavior approximating to a single trap response. The MoS2 MOSFET with 4-layer MoS2 and 8 nm HfO2 gave Dit values ranging from 2 × 1011 to 2 × 1013 cm–2 eV–1 across the energy range corresponding to depletion near the HfO2/MoS2 interface. The gate current was below 10–7 A/cm2 across the full bias sweep for both samples indicating continuous HfO2 films resulting from the combined UV ozone and HfO2 deposition process. The results demonstrated that impedance spectroscopy applied to relatively simple top-gated transistor test structures provides an approach to investigate electrically active defects at the HfO2/MoS2 interface and should be applicable to alternative TMD materials, surface treatments, and gate oxides as an interface defect metrology tool in the development of TMD-based MOSFETs

Dual-gate MoS2 transistors with sub-10 nm top-gate high-k dielectrics

High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 and an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion of the thin Al2O3 layer. The results show that the Al2O3 buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS2/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al2O3 dielectric demonstrate a near-ideal subthreshold swing of ∼60 mV/dec and a high field effect mobility of 100 cm2/V·s

Understanding the impact of annealing on interface and border traps in the Cr/HfO2/Al2O3/MoS2 system

Top-gated, few-layer MoS2 transistors with HfO2 (6 nm)/Al2O3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance–voltage (C–V) measurements to study electrically active traps (Dit) in the vicinity of the Al2O3/MoS2 interface. Devices with low Dit and high Dit are both observed in C–V characterization, and the impact of H2/N2 forming gas annealing at 300 and 400 °C on the Dit density and distribution is studied. A 300 °C anneal is able to reduce the Dit significantly, while the 400 °C anneal increases defects in the gate stack. Simulation with modeled defects suggests a sizable decrease in Dit, half the amount of positive fixed charge in the dielectric, and slightly increased unintentional doping in MoS2 after a 300 °C anneal. In the as-fabricated devices displaying high Dit levels, the energy distribution of the Dit located at the Al2O3/MoS2 interface is continuous from the conduction band edge of MoS2 down to 0.13–0.35 eV below the conduction band edge. A plausible Dit origin in our experiments could come from the unexpected oxygen atoms that fill the sulfur vacancies during the UV–O3 functionalization treatment. The border trap concentration in Al2O3 is the same, both before and after the anneal, suggesting a different origin of the border traps, possibly due to the low-temperature atomic-layer-deposited process

Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance - voltage analysis

Abstract Border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C-V characterization. Frequency dependent C-V data shows dispersion in both the depletion and accumulation regions for the MoS2 devices.The border trap density is extracted with a distributed model, and interface traps are analyzed using the high-low frequency and multi-frequency methods. The physical origins of interface traps appear to be caused by impurities/defects in the MoS2 layers, performing as band tail states, while the border traps are associated with the dielectric, likely a consequence of the low-temperature deposition. This work provides a method of using multiple C-V measurements and analysis techniques to analyze the behavior of high-k/TMD gate stacks and deconvolute border traps from interface traps

Engineering the interface chemistry for scandium electron contacts in WSe2 transistors and diodes

Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS2, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe2 transistors with impressive subthreshold slope (109 mV dec−1) and I ON/I OFF (106) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe2 in situ before metallization, which minimizes subsequent reactions between Sc and WSe2. Post metallization anneals in reducing environments (UHV, forming gas) degrade the I ON/I OFF by ~103 and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe2, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe2 layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe2 Fermi level around individual Sc atoms in the WSe2 lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe2 transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe2