Control System for Hydraulic Hybrid Propulsion System

A control system for a Hydraulic Hybrid Propulsion System (HHPS) is proposed and specified. Performance of the control system is evaluated by means of digital computer simulation of the total propulsion system. In order to accomplish this, analytical models of HHPS components are developed. The simulation consists of a city bus negotiating a typical driving cycle developed for this purpose on the basis of actual city bus cycle data. Performance of the control system is found to be satisfactory in all phases of driving cycle with the exception of transition from acceleration to cruise

Floating Voltage Sensing Based on Ceramic Capacitor Ferroelectric Derating

This paper presents methods allowing to provide galvanically isolated DC voltage measurement with nearly infinite input impedance. Measurement is based on a ferroelectric effect, creating hysteretic capacitance vs. bias- voltage (C-V) dependence of the ordinary multilayer ceramic capacitors. Voltage measurement is based on AC impedance sensing of a high-density multilayer ceramic capacitor and comparing with ground-referred matched capacitor with corresponding DC bias voltage. Corresponding DC bias voltage is provided by negative impedance converter and a feedback network. Despite finite accuracy (~1%), voltage sensing performed by a capacitor can be advantageous as it allows to implement AC (high-voltage) coupling, and presents nearly ideal infinite input impedance. This can be beneficial in a variety of applications e.g. in power management systems, energy harvesting applications, or scientific instrumentation

Regulated Cascode Current Mirror with Improved Voltage Swing

This paper presents a simple and easy-to-use method allowing to improve output swing of regulated cascode CMOS current mirror with short channel devices. It is based on matched offset voltage generators, implemented simultaneously at the input and output of the current mirror. These voltage generators translate the drain voltages of the reference and source transistors to the saturation voltage VDSAT, i.e. to minimal level, ensuring high output resistance of the cascode. The design aims to provide a nanosecond current generator for optical laser source, with fast short channel devices facilitating the integration. This paper presents a concept of circuit implementation, a mathematical description of the optimal value of voltage offset, and simulation results in 40nm process

Series Capacitor Dual-output DC/DC Converter and Power Inverter with Reduced Switching Voltage and Stress on Switching Devices

This paper presents seriescapacitordual inductorswitching power convertorthat features dual output capabilityand reduced VDD/2 switching voltage. Thedual output capabilityallowscircuit tobe configured as DC/DCpower converter with two distinct outputs, or aDC/ACpower inverter. The output voltage range is limited to VDD/2, and it is therefore suitable for applicationswith high downscale ratio. The structureis based on a series capacitortopologywhich features reduced VDD/2 switching voltage for bothchannelsand also reduced VDD/2 maximal ratings of switches and series capacitor. Thisreduces considerably the active area and dynamic (switching) power lossesof the converter. Structure also feauturespassive flying capacitor voltage balancing ensured by one reducedauxiliary capacitor

Dynamic duty-cycle limitation of the boost DC/DC converter allowing maximal output power operations

This paper describes the concept of the dynamic duty-cycle limiter of the boost dc-dc converter. Duty-cycle limitation in boost converters is usually used to protect the bottom switch against an excessive current, and also to avoid instability occurring at high duty-cycle operations. Compared to fixed limitation, dynamic limiter enables to detect and maintain maximal possible output voltage V MAX , when desired output voltage cannot be provided e.g. due to excessive load current or increased resistance of the switches. This feature allows to extend the operation range of the converter and powered device. Developed method applies to low power converters, and it is based on the power balance condition detection circuit. This detection is realized via simple and low consumption voltage sensing. Paper presents description of the method, circuit implementation and shows simulated results obtained with integrated 0.13μm CMOS boost dc-dc converter

Voltage Offset Compensation in CMOS OTAs: Novel Approaches for Temperature Drift Improvement

International audienceThis invited paper introduces novel approaches for trimming the voltage offset of CMOS operational amplifiers and comparators. The presented methods can be applied either to a one-time trimming during production testing, or via periodic calibration during circuit operation. The primary focus of this paper is to optimize the temperature drift of the trimmed and untrimmed offset voltage, VOS. The paper discusses various approaches to achieve this goal, including a) constant current injection, b) MOS physical size programming, and c) tail offset voltage trimming. Furthermore, the paper introduces new techniques that enhance temperature drift performance: d) temperature compensated current offset injection, e) temperature compensated active load trimming, f) constant-resistance tail offset voltage trimming, and g) series input-referred voltage generator. Additionally, the paper introduces the concept of transconductance temperature characteristic dumping, which has the potential to improve the residual temperature drift of the OTA. Simulation in 130nm CMOS demonstrating the effectiveness of the presented methods are provided

Floating Voltage Sensing Based on Ceramic Capacitor Ferroelectric Derating

This paper presents methods allowing to provide galvanically isolated DC voltage measurement with nearly infinite input impedance. Measurement is based on a ferroelectric effect, creating hysteretic capacitance vs. bias- voltage (C-V) dependence of the ordinary multilayer ceramic capacitors. Voltage measurement is based on AC impedance sensing of a high-density multilayer ceramic capacitor and comparing with ground-referred matched capacitor with corresponding DC bias voltage. Corresponding DC bias voltage is provided by negative impedance converter and a feedback network. Despite finite accuracy (~1%), voltage sensing performed by a capacitor can be advantageous as it allows to implement AC (high-voltage) coupling, and presents nearly ideal infinite input impedance. This can be beneficial in a variety of applications e.g. in power management systems, energy harvesting applications, or scientific instrumentation

Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors

This PhD thesis deals with the design of a CMOS integrated circuit as a readout electronic for the THz bolometric detectors, either semiconductor or high-Tc superconductor. We study a chain of the analog signal processing composed of the differential fixed-gain amplifier for the temperature range of 40 to 400K, as well as of the high dynamic range low-pass active frequency filter. As the optimal amplifier configuration, a feedback-free architecture was selected in order to reach high frequency bandwidth (17MHz for gain 40dB), low quiescent current (Iq=2mA) and high input impedance. In this amplifier, the gain is set in the CMOS structure via two different methods and the accuracy is verified by wide-temperature measurements of the fabricated integrated circuit. Consequently, the behaviour of the frequency filters is examined namely in the stopband, aiming to increase the maximal cut-off frequency. As an outcome, two structures with low influence of real active elements' parameters are designed: improved type-II Sallen-Key and the structure based on the CCII- current conveyor. In the last part, the integrated CCII- with very low output impedance is presented.Cette thèse porte sur la conception d'un circuit intégré CMOS pour l'électronique de lecture de capteurs bolométriques à base de semiconducteurs ou supraconducteurs haute-température. Dans ce manuscrit, une chaîne de traitement du signal est étudiée. Elle est composée d'un amplificateur différentiel à gain fixé pour des températures de 40 à 400K, ainsi que d'un filtre de fréquence passe-bas actif à haute dynamique. Une architecture optimale d'amplificateur est définie sans contre-réaction, permettant d'atteindre une large bande passante (17MHz pour un gain de 40dB), une consommation réduite (Iq = 2mA) et une haute impédance d'entrée. Afin de fixer le gain avec précision dans la structure CMOS, deux méthodes différentes sont présentées et vérifiées sur un circuit intégré. Par la suite, le comportement des filtres dans la bande d'atténuation est étudié afin d'augmenter la fréquence de coupure maximale. Deux structures avec une faible influence des éléments actifs « réels » sont conçues: le filtre Sallen-Key amélioré et la structure basée sur un convoyeur du courant CCII-. Enfin, nous présentons un CCII- intégré en CMOS ayant une très faible impédance de sortie