This paper presents a simple and easy-to-use
method allowing to improve output swing of regulated cascode
CMOS current mirror with short channel devices. It is based on
matched offset voltage generators, implemented simultaneously
at the input and output of the current mirror. These voltage
generators translate the drain voltages of the reference and
source transistors to the saturation voltage VDSAT, i.e. to minimal
level, ensuring high output resistance of the cascode. The design
aims to provide a nanosecond current generator for optical laser
source, with fast short channel devices facilitating the
integration. This paper presents a concept of circuit
implementation, a mathematical description of the optimal
value of voltage offset, and simulation results in 40nm process

Michal, Vratislav

DSpace at University of West Bohemia

ISBN 978-80-261-1049-1, © University of West Bohemia, 2022 Regulated Cascode Current Mirror with Improved Voltage Swing  Vratislav Michal  STMicroelectronics, Imaging division, 12 rue Julles Horowitz, Grenoble, France vratislav.michal@st.com Abstract—This paper presents a simple and easy-to-use method allowing to improve output swing of regulated cascode CMOS current mirror with short channel devices. It is based on matched offset voltage generators, implemented simultaneously at the input and output of the current mirror. These voltage generators translate the drain voltages of the reference and source transistors to the saturation voltage VDSAT, i.e. to minimal level, ensuring high output resistance of the cascode. The design aims to provide a nanosecond current generator for optical laser source, with fast short channel devices facilitating the integration. This paper presents a concept of circuit implementation, a mathematical description of the optimal value of voltage offset, and simulation results in 40nm process. Keywords—CMOS current mirror, high-swing cascode, regulated cascode, fast current pulse generator. I. INTRODUCTIONRecent trends in the custom IC integration cover hybrid implementation of the analog and digital VLSI circuits in sub-µm process, allowing to reduce area and power consumption of digital blocks. However, it involves complicated designs of analog circuits and may result in declining analog performances. This occurs mainly due to poor DC analog performances of sub-µm devices. Typical sub-µm CMOS process contains several voltage-rated devices. GO1 (GO states for gate oxide thickness) are fast short-channel and low voltage devices, whereas GO2 are larger medium voltage devices designed to implement analog functions. Generally, GO2 transistor have better analog performances, except for parasitic capacitances and thus the speed. Using transistors with several tens of nm channel length results in very fast operations, but typically poor DC performances. Transistor output resistance rDS is particularly affected by short channel. It is well known that the channel length modulation λ[V-1] is responsible for limited output resistance of an MOSFET transistor in saturation [1]. It is inversely proportional to the channel length L:  ELV Lλ∆≈ (1) where VE is the approximation of Early voltage, L is the channel length and ΔL is the length of pinch-off region. Small signal output resistance rDS can be expressed from λ: 1DSDrIλ= (2) Low output resistance of the current mirror decreases accuracy of the output current. It creates a dependency between output current IOUT and DC voltage VOUT. Similarly,978-1-6654-9482-3/22/$31.00 ©2022 IEEE W = 5µmIREF = 1.0µAL = 0.3µm (GO2 device)rout = 1.5MΩ L = 60nm (GO1 device)rout = 510kΩ Ohmic regionsaturation regionVDSATVDSATIREF = 1µAMOUTMREFIOUTVDSVDS  (mV)I OUT   (µA)Ideal I/V characteristicFig. 1. Comparison of the output characteristic for a simple current mirror for GO1 and GO2 MOS transistors limited rDS reduces voltage gain of analog building blocks such as the comparators or operational amplifiers [1].  Output I/V characteristic of a simple non-cascoded current mirror with W = 5µm is shown on example in Fig. 1. Output characteristic for transistors with L = 0.3µm is relatively flat (high rout), whereas it presents inconvenient high slope (low rout) for short-channel device with L = 60nm. As we can see, transition between ohmic and saturation region for short channel device is ambiguous. IAUX IREFMREFMBMCASCVTH+VOVβ·IAUXα· IREFα · MREFβ·MBMCASCVDS _REF VDS _REFVDDGNDMCASCMREFIREFVDDα· IREFGNDVBα · MREFVTH+VOVa) b)VDS _O UTSmall VDSVOU TFig. 2. a) standard “passive” cascode, b) regulated (Sackinger) cascode [2]. Increasing output impedance is typically provided either by increasing the channel length (1), (2), or by use of cascode structure. Whilst increase of the channel length allows to reach high output swing, it also presents poor AC performance related to excessive transistor area. On the other hand, standard “passive” cascode as shown in Fig. 2. a) increases output resistance rout as given by a general cascode formula [1]: ( )( ) ( ) ( ) ( )11out DS casc m casc DS casc DS refr r g r r>>= + +144424443(3) where gm and rDS are the transconductance and output 2022 International Conference on Applied Electronics (AE) | 978-1-6654-9482-3/22/$31.00 ©2022 IEEE | DOI: 10.1109/AE54730.2022.9920096Authorized licensed use limited to: Univ of West Bohemia in Pilsen. Downloaded on November 04,2022 at 08:54:26 UTC from IEEE Xplore.  Restrictions apply.   resistances of respective transistors MCAS and MREF. In “passive” cascode shown in Fig. 2 a), MCASC acts as a source follower and stabilizes the drain voltage of MREF. It means that VDS_OUT is maintained roughly constant by gm of the cascode transistor. When considering an example of very low rDS for 60nm device from Fig. 1, improvement (3) provided by “passive” cascode is insufficient, and the cascode presents non-negligible dependence between IOUT on VOUT. With drain voltage stabilization realized by source follower Fig. 2 a) being insufficient for short-channel devices, an active loop regulating VDS voltage of MREF can provide very high stability. Regulating loop can be provided either by an OTA [1], or in a simple way by a regulated cascode [2] shown in Fig. 2 b). Circuit of regulated cascode can reach very high speed. This is mainly thanks to the simplicity, as well as to the use of short-channel devices in the feedback loop.  In the circuit of regulated cascode shown in Fig. 2 b), reference and source branches contain supplementary transistors MB and small auxiliary bias currents IAUX. Transistors MB with current source IAUX create a gain stage that regulates VDS of MREF to the value of gate-source voltage of MB. This voltage is given by the geometry W/L of MB and value of the bias current IAUX:  ( ),2AUXGS B TH OV THn p OXI LV V V VC Wµ= + = +   (4) where VTH is the threshold voltage, VOV overdrive voltage VOV = VGS − VTH,   is the carrier mobility,   the gate capacitance and W/L the aspect ratio of transistor MB. Deviation from regulation target VDS_REF ≠ VGS(B) is compensated by the feedback loop via gate voltage of MCASC. It results that output impedance rout of passive cascode (3) is amplified by the voltage gain of transistor MB. II. HIGH-SWING REGULATED CASCODE In low voltage CMOS design, the target is to ensure operations of the current mirrors in a wide voltage range, namely towards low VDS voltages. General approach to maximize the output voltage swing of the cascode Fig. 2 a) is to set voltage Vb to an optimal value allowing VDS of MREF to be equal to its saturated voltage VDSAT. At this voltage, transistor operates between linear and saturated regions and reaches decent rDS. Such performance can be achieved e.g. by Sooch cascode [3], Brooks - Rybicki cascode [4] or others known structures mentioned e.g. in [1].  By definition, VDS = VDSAT places the transistor between linear (ohmic) and saturated regime. In first-order approximation  VDSAT is given by a simple formula:  DSAT GS THV V V= −   (5) Even though this equation is sufficient for long-channel devices, it is a rough approximation for short channel devices. On the other hand, definition of VDSAT for short-channel devices is very ambiguous (see Fig. 1). It results that some acceptable inaccuracy have negligible impact on resulting rDS. Compared to optimal VDSAT of high-swing cascode from Fig. 2 a), drain voltage of regulated cascode Fig. 2 b) is high, because it contains full VTH of transistor MB.  IAUX IREFMREFMBMCASCVTH + VOVβ·IAUXα· IREFα · MREFβ·MBMCASCVTH + VOVVD_ REF VD_OU TVDDGNDVosVosImproved VDSVOU T Fig. 3. Increasing output voltage swing of regulated cascode by setting VDS(REF) to VDSAT. Voltage source VOS are set to ~VTH(B). This inconvenient biasing decreases output voltage swing by several hundreds of mV. In addition, high drain voltage of MREF, and comparable drain voltage of MCASC result in small VDS of MCAS of the left reference branch (see Fig. 2 b). Due to small VDS, MCASC can drop into ohmic regime, and thus decrease gain of the feedback loop of the regulated cascode. A. Regulated Cascode with Improved Swing An improvement of the voltage swing of regulated cascode is presented in [5]. It replaces the gain stage MB - IAUX in Fig. 2 b) by a self-biased inverter-based push-pool amplifier. Besides uncontrolled bias current, this solution allows to improve the voltage swing by decreasing VDS of the reference transistor. Unfortunately, VDS setting in [5] relies on matching of PMOS and NMOS transistors. Matching of PMOS and NMOS is process, supply voltage, and temperature sensitive, and results in inaccurate setting of MREF VDS voltage.  Similarly as previously discussed for passive high swing-cascode counterpart, the approach used in this paper is to accurately regulate the drain voltage of MREF to VDSAT. This is achieved by adding supplementary accurate voltage generator VOS between the gate of MB and drain of MREF, as shown in Fig. 3. This technique allows to accurately control VDSAT of MREF, but also maintains MCAS in saturation with large saturation margin.  Example of DC characteristic of Fig. 3 modified cascode is shown in Fig. 4 for various VOS. Here, VDS_REF > VDSAT reaches decent rout but limited output voltage swing, whereas VDS < VDSAT results in poor output resistance due to MREF operating in the ohmic region. It can be observed that VDS = VDSAT is the best tradeoff to maximize rout and voltage swing.  VOUT   (V)I OUT   (µA)VDS,sat = 64, 110, 158, 204, 252, 300, 346 (mV)Single transistor CM (10/0.06 µm) “passive” cascode (10/0.06 µm)Regulated cascodeVDSAT of MREF = 128mVGain of voltage swing: 220mVMREF in ohmic regimeOptimal VOS Fig. 4. Comparison of regulated cascode for various VOS, comparison with single-transistor current mirror Fig. 1 and “passive” cascode from Fig. 2 a). Authorized licensed use limited to: Univ of West Bohemia in Pilsen. Downloaded on November 04,2022 at 08:54:26 UTC from IEEE Xplore.  Restrictions apply.   B. VOS Voltage Generator In order to satisfy the condition VDS_REF = VDSAT over all PVT (process-voltage-temperature) variations, voltage generator VOS, depending on the same physical parameters as VDSAT, needs to be implemented.  IAUX IREFMREFMBMCASCVTH(B)+VOV(B )VDS _REFVDDGNDVosVDSAT VGS(R EF) Fig. 5. Reference part of regulated cascode from Fig. 2 b) allowing to determine optimal value of the offset voltage VOS.   Circuit shown in Fig. 5 allows to determine the value of VOS required to establish VDS_REF = VDSAT. VGS voltage of MB can be written as a sum of the threshold voltage and overdrive voltage VOV = IAUX/gm:  ( ) ( )( )AUXGS B TH Bm BIV Vg= +   (6) And this gate voltage is equal to:  ( ) ( )GS B DSAT REF OSV V V= +   (7) While VDSAT(REF) is equal to 	 ()⁄ , VOS can be written as:  ( )( ) ( )AUX REFOS TH Bm B m REFI IV Vg g= + −   (8) If geometry and bias currents are chosen in a way that transistors MB and MREF have identical VTH and VOV, last terms in (7) cancels and VOS can be written as:  ( )OS TH BV V=   (9) This renders the desired value of VOS allowing to set VDS_REF to VDSAT across PVT corners. Channel width WB of transistor MB can be found from general 1st order equation for transconductance gm:  m P DWg K IL=   (10) where KP is µn,pCOX. Considering identical channel length LB and LREF, VDS_REF and VDS_OUT can be set to VDSAT by setting VOS = VTH(B) (9) and channel width ratio:  REF REFB AUXW IW I=   (11) Identical LB and LREF result from the requirement on identical VT of transistors MREF and MB. This matching should be maintained regardless PVT condition. It means that short-channel device MREF resulting from the high-speed requirement implies short channel device MB. One can remark that using short channel MB decreases the gain of the regulating loop due to reduced rDS(MB) (2). However, even relatively small gain of this loop provides an interesting improvement compared to cascode shown in Fig. 2 a). IAUX(CASCODED)IREFMREFMBMCASCVTH(B)+VOV(B)VDS _REFGNDVosVDSATMBMBMBMB13MBHigh gainVBIAUX Fig. 6. Improving of the feedback-loop gain by cascading MB transistor. If gain enhancement obtained with short-channel MB is insufficient, passive high swing cascode can be added to increase rDS of MB. This is conceptually shown in Fig. 6 with example of Sooch cascode [3]. This additional cascode has very limited impact to overall speed but allows to increase gain of the regulated cascode loop by more than 20dB.  III. IMPLEMENTATION OF IMPROVED REGULATED CASCODE  VOS = VTH(B) can be generated by an additional diode-mounted transistor   driving very small current IOS. Very small current in auxiliary transistor   minimizes its overdrive voltage VOV (4) in a way that VDS ≈ VTH(B) required by (9). Additionally, small IOS reduces errors from IOS, such as low rout, limited output swing or temperature drift. A. Regulated Cascode with Diode-mounted Transistors  A simple method to implement VOS = VTH(B) is shown in Fig. 7. Here, diode mounted transistors   are connected as VOS voltage generators and are bypassed by COS. Voltage VOS is generated by a very small offset current IOS according to (4). Decoupling capacitors COS reduce impedance of VOS voltage generator, allowing to maintain constant voltage even during transient events. It is to be noted, that current IOS biasing transistor   is added to IREF on the reference side, and simultaneously subtracted from IOUT on the output of the cascode. In the case of unitary current-mirror ratio 1:1, this offset is cancelled, as it is present on both sides. If the cancellation cannot be achieved e.g. by appropriate scaling of right   and IOS, current offset can be compensated by bottom   current sink shown in Fig. 7. As VDS of MREF is voluntarily kept low,    current is subtracted from IREF at the drain of transistor MCASC. This slightly increases drain voltage of   that facilitates its implementation. Alternatively, right side   can be omitted if value of IOS is negligible compared to IOUT.  IAUX IREFMREFMBMCASCβ·IAUXIOUT = α· IREFα · MREFβ·MBMCASCVDS_REF VDS_OUTIOS IOSIOSIOSCosCosMBMBVDDGNDImproved VDS Fig. 7. Implementation of regulated cascode with improved swing. Diode-connected transistors act as VOS voltage sources producing ~VTH(B) voltages. Authorized licensed use limited to: Univ of West Bohemia in Pilsen. Downloaded on November 04,2022 at 08:54:26 UTC from IEEE Xplore.  Restrictions apply.   B. Current Conveyor with Resistive VOS generators Using floating transistors  , allowing to improve the output swing, is sufficient in majority of cases. However, to eliminate the bulk effect of  , transistors MB shall be implemented in isolated wells. This increases parasitic coupling to GND and slows the current-mirror transient response. If the speed limitation becomes dominant, transistors can be replaced by matched resistors biased by a CCII± current conveyor. This structure is shown in Fig. 8.  CCII± current conveyor reproduces input VOS voltage from terminal Y to the voltage output terminal X. The current through reference resistor ROS at terminal X is reproduced either in positive or negative polarity to the current outputs Z± [6]. These currents create matched voltage drops VOS on ROS in the structure of regulated cascode. Similarly to previous implementation, negative current sink   needs to be implemented only if the compensation of IOS current in the structure is needed.   IAUX IREFMREFMBMCASCβ·IAUXα· IREFα · MREFβ·MBMCASCVDS_REF VDS_OUTIOSRos RosCosCosMBIOSCCII± RosYXZ’Z’’Z’’Z’++--VDDGND-IOSVOSVOS VOSVOS Fig. 8. Implementation of VOS generator by CCII± and matched resistors. IV. SIMULATION RESULTS Main purpose of the simulation is to verify that VDS of MREF is close to VDSAT for expected PVT operating scenarios, and that output DC characteristic has maximal voltage swing and output resistance. This verification was done by DC simulations on regulated cascode with L = 60nm short-channel transistors and 10µA reference current. Simulation outcomes are shown for three PVT scenarios in Fig. 9 a,b,c) detailing output I/V characteristic. Fig. 9 a) corresponds to the typical operating condition at room temperature, Fig. 9 b) represents high temperature scenario where the transistor model parameters were adjusted to represent slow operating conditions, and Fig. 9 c) represents low temperature operations with fast adjustment of transistor models. In all cases, current mirror reaching optimal output swing vs. output resistance rout can be observed. CONCLUSION This paper presents improvement of regulated cascode structure to maximize the output voltage swing across a wide range of operating conditions. The presented circuit allows to use fast GO1 short-channel devices and therefore to optimize the transient response speed of the current mirror. Optimization is achieved by introducing accurate offset to the feedback loop of regulated cascode. This permits to translate regulated VDS voltage of the reference transistor to the optimal value VDSAT. Demonstrated good stability of VDSAT, across PVT corners enable employment of the structure in high-performances circuits, such as the nanosecond laser current source for optical communications.  VOS = 300, 250, 200, 150, 100 50, 0 (mV)MREF in ohmic regimeVOUT   (V)I OUT   (µA)Typical condition, 27ºCGain of voltage swing: 200mVImproved regulated cascode MREF in ohmic regimeVOUT   (V)I OUT   (µA)Slow scenario, 150ºCGain of voltage swing: 130mVImproved regulated cascodeVOS = 200, 150, 100 50, 0 (mV) MREF in ohmic regimeVOUT   (V)I OUT   (µA)Fast scenario, -40ºCGain of voltage swing: 220mVImproved regulated cascodeVOS = 300, 250,200, 150, 100 50, 0 (mV) Fig. 9. Comparison of the output characteristic for modified regulated cascode with IREF = 10µA, IOS = 50nA, IAUX = 2µA and LB,REF = 60nm. REFERENCES [1] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” Book, Oxford university pres, 2019. [2] E. Sackinger, “A high-swing, high-impedance MOS cascode circuit,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 289 – 298, 1990 [3] N. S. Sooch, “MOS Cascode current mirror,” US pattent US4550284. [4] T. L. Brooks, M. A. Rybicki, “Self-biased cascode current mirror having high voltage swing and low power consumption,” U.S. Patent 5,359,296  [5] A. Srivastava, S.S. Rajput, G.K. Sharma, “Low voltage regulated cascode current mirrors suitable for sub-1V operation,” 2010 IEEE Asia Pacific Conference on Circuits and Systems  [6] D. Biolek et al., “Active Elements for Analog Signal Processing: Classification, Review, and New Proposals,” Radioengineering, 2008. Authorized licensed use limited to: Univ of West Bohemia in Pilsen. Downloaded on November 04,2022 at 08:54:26 UTC from IEEE Xplore.  Restrictions apply.    Authorized licensed use limited to: Univ of West Bohemia in Pilsen. Downloaded on November 04,2022 at 08:54:26 UTC from IEEE Xplore.  Restrictions apply. 

Regulated Cascode Current Mirror with Improved Voltage Swing

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Regulated Cascode Current Mirror with Improved Voltage Swing

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