A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number

[EN] The computation of the arctangent of a complex number, i.e., the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In this brief, we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a first stage that performs a coarse approximation of the atan2 function and a second stage that improves the output accuracy by means of a lookup table. We present results for fixed-point implementations in a field-programmable gate array device, all of them guaranteeing last-bit accuracy, which provide an advantage in latency, speed, and use of resources, when compared with well-established fixed-point options.This work was supported by the Spanish Ministerio de Economia y Competitividad and FEDER under Grant TEC2015-70858-C2-2-R.Torres Carot, V.; Valls Coquillat, J. (2017). A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25(9):2663-2667. https://doi.org/10.1109/TVLSI.2017.2700519S2663266725

Effects of a Tapering Period on Physical Condition in Soccer Players

The aim of this research was to analyze the effects of a 2-week step tapering period on lower-limb muscle power, change of direction (COD) and acceleration capacities, and on the stress-recovery state in an amateur soccer team. Twenty-two male players were included in the study. After a 6-week progressive training, the sample was divided into experimental group (EG) (n = 11), which did a 2-week period of taper in which training volume was 50% reduced (intensity was kept high) and control group (CG) (n = 11), which kept on with the training. Muscle power (countermovement jump test), acceleration (10-m sprint test), COD (Illinois test), and stress and recovery perceptions (RESTQ questionnaire) were evaluated before training, at the end of it (pretapering, PRE-TP) and after the tapering period (posttapering, POST-TP). After the taper, the EG in comparison with the CG showed significantly improved power (1,029.71 ± 108.51 W·kg−1 vs. 1,084.21 ± 110.87 W·kg−1; p ≤ 0.01), acceleration (1.72 ± 0.09 seconds vs. 1.67 ± 0.07 seconds; p ≤ 0.05), and lower stress levels (1.9 ± 0.5 vs. 1.6 ± 0.5; p ≤ 0.01) (PRE-TP vs. POST-TP, respectively). Change of direction did not show significant changes. In conclusion, a 2-week step tapering program was found to be an effective periodization strategy to increase muscle power and acceleration, and to reduce stress perception in soccer amateur players

Fast- and Low-Complexity atan2(a,b) Approximation

[EN] This article presents a new entry to the class of published algorithms for the fast computation of the arctangent of a complex number. Our method uses a look-up table (LUT) to reduce computational errors. We also show how to convert a large-sized LUT addressed by two variables to an equivalent-performance smaller-sized LUT addressed by only one variable. In addition, we demonstrate how and why the use of follow-on LUTs applied to other simple arctan algorithms produce unexpected and interesting results.This work is funded by the Spanish Ministerio de Economía y Competitividad and FEDER under grant TEC2015-70858-C2-2-R.Torres Carot, V.; Valls Coquillat, J.; Lyons, R. (2017). Fast- and Low-Complexity atan2(a,b) Approximation. IEEE Signal Processing Magazine. 34(6):164-169. https://doi.org/10.1109/MSP.2017.2730898S16416934

Is Leader Developing Behavior related to Employees' Health Complaints? A Multilevel Investigation

The goals of this study were to ascertain whether a specific leadership behavior (developing subordinates) is related to employees' health complaints and determine some of the underlying mechanisms involved. The hypothesized relationships were investigated in a sample composed of 538 employees working in 170 work-units of a public regional health service. Multilevel structural equation modeling was used to estimate the hypothesized relationships at the individual and work-unit levels. Results obtained at the individual level showed, as expected, that leader developing behavior was negatively related to employees' health complaints through two mediators: organizational commitment and emotional exhaustion. At the work-unit level, leader developing behavior was not related to employees' health complaints. Our findings uncover some of the mechanisms linking leader developing behavior and employees' health complaints at the individual level, show that the observed relationships cannot be generalized across levels, and have implications for the Job Demands-Resources theory

Optimised CORDIC-based atan2 computation for FPGA implementations

This paper is a postprint of a paper submitted to and accepted for publication in Electronics Letters and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library[EN] A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture.This work was funded by the Spanish Ministerio de Economia y Competitividad and FEDER under the grant TEC2015-70858-C2-2-R.Torres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ. (2017). Optimised CORDIC-based atan2 computation for FPGA implementations. Electronics Letters. 53(19):1296-1298. https://doi.org/10.1049/el.2017.2090S12961298531

Tratamiento digital de señales. Problemas y ejercicios resueltos

El documento es un libro de problemas y ejercicios de Tratamiento Digital de Señales. Este libro publicado por Prentice-Hall en 2003, se ofrece actualmente como recurso de acceso abierto tras su descatalogación. En él se ofrecen ejemplos de problemas y ejercicios resueltos de Tratamiento Digital de Señales, a los que previamente se introduce la base teórica suficiente como para seguir el desarrollo del texto. El contenido es el siguiente: Señales y sistemas en tiempo discreto; Análisis frecuencial de señales y sistemas; Transformada z; Realización de sistemas en tiempo discreto; Efectos de longitud de palabra finita; Diseño de filtros digitales; Sistemas adaptativos.That document is a book of problems and exercices of Digital Signal Processing. This book was published in 2003 by Prentice-Hall, and is now offered as an Open Acces resource after gotten out of catalog. It shows the resolution of problems and exercices of Digital Signal Processing, with a previous theoric introduction, enough to follow the text. The contents are: Discrete signals and systems; Frequencial analysis of signals and systems; Z Transform; Discrete-time systems implementation; Finite word-lenth effects; Digital filters design; Adaptative systems

¿Un nuevo paradigma para la enseñanza de la historia? Los problemas reales y las polémicas interesadas al respecto en España y en el contexto del mundo occidental

La complejidad de la situación presente respecto de la enseñanza escolar de la historia, aparte de los muy importantes cambios historiográficos habidos en los últimos decenios y de las nuevas finalidades asignadas a su enseñanza escolar, se ha visto aún más destacada por el interés habido, por parte de ciertos sectores políticos y culturales, de establecer unos contenidos y un tipo de enseñanza de la historia que han provocado una fuerte polémica. Para intentar contextualizar este panorama general, en un primer apartado se aborda sintéticamente las características principales de la polémica habida sobre la enseñanza de la historia en España, contrastando las valoraciones expresadas por diversas instancias oficiales con los resultados obtenidos en algunas de las investigaciones empíricas existentes. En segundo lugar se esboza los cambios y las continuidades que tanto el profesorado como los manuales escolares han presentado durante los últimos 10-20 años. En la parte final se muestran las dificultades presentes de la enseñanza de la historia y las pautas de posible superación de las mismas (un intento de nuevo paradigma educativo), en conformidad con la investigación didáctica internacionalThe complexity of today’s situation regarding history school teaching, besides the very important historiographic changes undergone in the past decades and the new purposes adscribed to history school teaching, has been even more highlighted due to the interest of some political and cultural groups in establishing some contents and a type of history teaching that have been the subject of controversy. To try to contextualize this general view, in the first section we systematically tackle the main characteristics of the controversy arisen regarding history teaching in Spain, contrasting the views expressed by several official authorities with the results obtained in some of the existing empirical researches. Secondly, the changes and the continuity that both teachers and school books have maintained during the past 10-20 years are outlined. In the final part, today’s difficulties in history teaching and the guidelines to overcome them (a new didactic paradigm attempt) in accordance with the international didactic research are shownS

Hardware Architecture of a QAM Receiver for Short-Range Optical Communications

[EN] Short-reach optical fiber communications systems aim to achieve high throughput, in the order of tens of Gbps. The implementation of these high-speed systems requires parallel processing, which makes low-complexity designs of their subsystems a key to the successful large-scale deployment of this technology. Half-Cycle Nyquist Subcarrier Modulation (HC-SCM) was originally suggested for these systems with the goal of using as much bandwidth as possible and, therefore, achieving high communication rates. Recently, Oversampled Subcarrier Modulation (OVS-SCM) was proposed as an alternative more computational efficient than HC-SCM and also with a better spectral efficiency. This paper proposes a hardware-efficient architecture for an OVS-SCM receiver, which takes into account the inherent parallel processing of these systems. This receiver takes 16 samples in parallel from a 5 GSa/s analog-to-digital converter with a 3.2 GHz 3 dB bandwidth. Design solutions for the frame detection block, the mixer, the resampler, the fractional interpolator, the matched filter and the timing estimator are presented. Our results show that, compared to the HC-SCM receiver, this proposal reduces the computational load of the downconverter stages by 90%. FPGA implementation results are given to demonstrate that our proposal can be implemented in state-of-the-art devices.This work was supported in part by MCIN/AEI/10.13039/501100011033 under Grants RTI2018-101658-B100 and PID2021-126514OB-I00, and in part by the European Union through "ERDF Away of making Europe."Valls Coquillat, J.; Torres Carot, V.; Pérez Pascual, MA.; Almenar Terre, V. (2023). Hardware Architecture of a QAM Receiver for Short-Range Optical Communications. Journal of Lightwave Technology. 41(2):451-461. https://doi.org/10.1109/JLT.2022.321735745146141

Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

[EN] In this work, we present a new architecture for soft-decision Reed-Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of a that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a h = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true h = 5 and h = 6 LCC decoders, respectively. For example, our h = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.This research was funded by the Spanish Ministerio de Economia y Competitividad and FEDER grant number TEC2015-70858-C2-2-RTorres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ.; García Herrero, FM. (2019). Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. Electronics. 8(1):1-13. https://doi.org/10.3390/electronics8010010S11381Cideciyan, R., Gustlin, M., Li, M., Wang, J., & Wang, Z. (2013). Next generation backplane and copper cable challenges. IEEE Communications Magazine, 51(12), 130-136. doi:10.1109/mcom.2013.6685768Koetter, R., & Vardy, A. (2003). Algebraic soft-decision decoding of reed-solomon codes. IEEE Transactions on Information Theory, 49(11), 2809-2825. doi:10.1109/tit.2003.819332Sudan, M. (1997). Decoding of Reed Solomon Codes beyond the Error-Correction Bound. Journal of Complexity, 13(1), 180-193. doi:10.1006/jcom.1997.0439Guruswami, V., & Sudan, M. (1999). Improved decoding of Reed-Solomon and algebraic-geometry codes. IEEE Transactions on Information Theory, 45(6), 1757-1767. doi:10.1109/18.782097Jiang, J., & Narayanan, K. R. (2008). Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information. IEEE Transactions on Information Theory, 54(9), 3907-3928. doi:10.1109/tit.2008.928238Jiangli Zhu, Xinmiao Zhang, & Zhongfeng Wang. (2009). Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(11), 1602-1615. doi:10.1109/tvlsi.2008.2005575Jiangli Zhu, & Xinmiao Zhang. (2008). Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(10), 3050-3062. doi:10.1109/tcsi.2008.923169Zhongfeng Wang, & Jun Ma. (2006). High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(9), 937-950. doi:10.1109/tvlsi.2006.884046Zhang, X. (2006). Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1156-1161. doi:10.1109/tvlsi.2006.884177Xinmiao Zhang, & Parhi, K. K. (2005). Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(4), 413-426. doi:10.1109/tvlsi.2004.842914Bellorado, J., & Kavcic, A. (2010). Low-Complexity Soft-Decoding Algorithms for Reed–Solomon Codes—Part I: An Algebraic Soft-In Hard-Out Chase Decoder. IEEE Transactions on Information Theory, 56(3), 945-959. doi:10.1109/tit.2009.2039073García-Herrero, F., Valls, J., & Meher, P. K. (2011). High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits, Systems, and Signal Processing, 30(6), 1643-1669. doi:10.1007/s00034-011-9327-4Zhang, W., Wang, H., & Pan, B. (2013). Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(5), 974-978. doi:10.1109/tvlsi.2012.2197030Peng, X., Zhang, W., Ji, W., Liang, Z., & Liu, Y. (2015). Reduced-Complexity Multiplicity Assignment Algorithm and Architecture for Low-Complexity Chase Decoder of Reed-Solomon Codes. IEEE Communications Letters, 19(11), 1865-1868. doi:10.1109/lcomm.2015.2477495Lin, Y.-M., Hsu, C.-H., Chang, H.-C., & Lee, C.-Y. (2014). A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 2110-2118. doi:10.1109/tcsi.2014.2298282Wu, Y. (2015). New Scalable Decoder Architectures for Reed–Solomon Codes. IEEE Transactions on Communications, 63(8), 2741-2761. doi:10.1109/tcomm.2015.2445759Garcia-Herrero, F., Canet, M. J., Valls, J., & Meher, P. K. (2012). High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(3), 568-573. doi:10.1109/tvlsi.2010.210396