FAT-DBT engine (framework for application-tailorcd, co-designcd dynamic binary translation enginc)

Tese de Doutoramento em Engenharia Eletrónica e de Computadores (PDEEC)Dynamic binary translation (DBT) has emerged as an execution engine that monitors, modifies and possibly optimizes running applications for specific purposes. DBT is deployed as an execution layer between the application binary and the operating system or host-machine, which creates opportunities for collecting runtime information. Initially, DBT supported binary-level compatibility, but based on the collected runtime information, it also became popular for code instrumentation, ISA-virtualization and dynamic-optimization purposes. Building a DBT system brings many challenges, as it involves complex components integration and requires deep architectural level knowledge. Moreover, DBT incurs in significant overheads, mainly due to code decoding and translation, as well as execution along with general functionalities emulation. While initially conceived bearing in mind high-end architectures for performance demanding applications, such challenges become even more evident when directing DBT to embedded systems. The latter makes an effective deployment very challenging due to its complexity, tight constraints on memory, and limited performance and power. Legacy support and binary compatibility is a topic of relevant interest in such systems, due to their broad dissemination among industrial environments and wide utilization in sensing and monitoring processes, from yearly times, with considerable maintenance and replacement costs. To address such issues, this thesis intents to contribute with a solution that leverages an optimized and accelerated dynamic binary translator targeting resourceconstrained embedded systems while supporting legacy systems. The developed work allows to: (1) evaluate the potential of DBT for legacy support purposes on the resource-constrained embedded systems; (2) achieve a configurable DBT architecture specialized for resource-constrained embedded systems; (3) address DBT translation, execution and emulation overheads through the combination of software and hardware; and (4) promote DBT utilization as a legacy support tool for the industry as a end-product.A tradução binária dinâmica (TBD) emergiu como um motor de execução que permite a modificação e possível optimização de código executável para um determinado propósito. A TBD é integrada nos sistemas como uma camada de execução entre o código binário executável e o sistema operativo ou a máquina hospedeira alvo, o que origina oportunidades de recolha de informação de execução. A criação de um sistema de TBD traz consigo diversos desafios, uma vez que envolve a integração de componentes complexos e conhecimentos aprofundados das arquitecturas de processadores envolvidas. Ademais, a utilização de TBD gera diversos custos computacionais indirectos, maioritariamente devido à descodificação e tradução de código, bem como emulação de funcionalidades em geral. Considerando que a TBD foi inicialmente pensada para sistemas de gama alta, os desafios mencionados tornam-se ainda mais evidentes quando a mesma é aplicada em sistemas embebidos. Nesta área os limitados recursos de memória e os exigentes requisitos de desempenho e consumo energético,tornam uma implementação eficiente de TBD muito difícil de obter. Compatibilidade binária e suporte a código de legado são tópicos de interesse em sistemas embebidos, justificado pela ampla disseminação dos mesmos no meio industrial para tarefas de sensorização e monitorização ao longo dos tempos, reforçado pelos custos de manutenção adjacentes à sua utilização. Para endereçar os desafios descritos, nesta tese propõe-se uma solução para potencializar a tradução binária dinâmica, optimizada e com aceleração, para suporte a código de legado em sistemas embebidos de baixa gama. O trabalho permitiu (1) avaliar o potencial da TBD quando aplicada ao suporte a código de legado em sistemas embebidos de baixa gama; (2) a obtenção de uma arquitectura de TBD configurável e especializada para este tipo de sistemas; (3) reduzir os custos computacionais associados à tradução, execução e emulação, através do uso combinado de software e hardware; (4) e promover a utilização na industria de TBD como uma ferramenta de suporte a código de legado.This thesis was supported by a PhD scholarship from Fundação para a Ciência e Tecnologia, SFRH/BD/81681/201

Bases de dados em grafos: Contextualização e estudo exploratório

After several decades of great success and good services to organizations, relational database technology has been challenged by a new class of database technologies usually called NoSQL (Not only SQL). The recent developments in the area called Big Data contributed decisively to this situation, in which the traditional relational model began to present difficulties, due to the complexity and large volumes of data. Within this new class of databases, different proposals, with several origins and application areas, appeared in four groups, according to their data model: column oriented, document oriented, key-value and Graphs oriented. In particular, graph databases provide a set of characteristics to represent relationships between data that no other model can represent so well. As we live in a world where information is all connected, this database model has what it takes to be successful. In this way, some examples of graph database applications will be discussed as well as demonstrations of the facility to construct queries, which would be extremely complex if they were developed in SQL over relational databases.FCT - Fundação para a Ciência e a Tecnologia(UID/CEC/00319/2013

A hardware-assisted translation cache for dynamic binary translation in embedded systems

Approaches to Dynamic Binary Translation (DBT) on resource-constrained embedded systems are not straight forward, leading to several improvements and acceleration suggestions that rely on dedicated hardware. Software to hardware offloading is a common acceleration procedure used when software-only approaches do not meet the performance requirements, making such approach suitable to be successfully applied to DBT. This article approaches hardware offloading to address some limitations of an in-house DBT engine, the DBTOR, regarding its Translation Cache (TCache) management mechanism. The suggested approaches are non-intrusive to the target architecture, which cope with the commercial-off-the-shelf (COTS)-driven deployment of DBT for the resource-constrained embedded devices. This work proposes a TCache management hardware module that overpasses the linked list and hash table software-only approaches, resulting in a performance improvement of 25% and 26%, respectively..This work has been supported by COMPETE: POCI-01-0145-FEDER-007043 and FCT - Fundação para a Ciência e Tecnologia within the Project Scope: UID/CEC/00319/2013

MODELA DBT: Model-driven elaboration language applied to dynamic binary translation

Industrial solutions design is a highly complex topic due to the challenge of integrating multiple technologies into a single solution, the inherent complexity of the problems to be solved and also because the proposed solutions often require a great level of interoperability among their components and also the outside world. Dynamic Binary Translation has been used as a tool to deal with such interoperability issues, e.g., legacy support, virtualization and secure execution, among others. However its integration in the industry as an end-product is hampered by the intricate variability management required in this subject. To address these issues and in an attempt to power DBT utilization as an interoperability-providing tool, we propose a model-driven DSL modeling language for DBT architectures. The developed DSL proved to be efficient to model an in-house DBT engine, and MODELA DBT, a framework for ready-to-use DBT solutions was obtained. MODELA DBT provides design validation, easy configuration of customizable DBT parameters and components, as well as code generation features.This work has been supported by COMPETE: POCI-Ol-0145-FEDER-007043 and FCT - Fundação para a Ciência e figuration granularity, code generation efficiency and design verification. Tecnologia within the Project Scope: UID/CEC/00319/2013. F. Salgado is supported by FCT (grant SFRH/BD/81681/2011)

Pervasive gaps in Amazonian ecological research

Biodiversity loss is one of the main challenges of our time,1,2 and attempts to address it require a clear un derstanding of how ecological communities respond to environmental change across time and space.3,4 While the increasing availability of global databases on ecological communities has advanced our knowledge of biodiversity sensitivity to environmental changes,5–7 vast areas of the tropics remain understudied.8–11 In the American tropics, Amazonia stands out as the world’s most diverse rainforest and the primary source of Neotropical biodiversity,12 but it remains among the least known forests in America and is often underrepre sented in biodiversity databases.13–15 To worsen this situation, human-induced modifications16,17 may elim inate pieces of the Amazon’s biodiversity puzzle before we can use them to understand how ecological com munities are responding. To increase generalization and applicability of biodiversity knowledge,18,19 it is thus crucial to reduce biases in ecological research, particularly in regions projected to face the most pronounced environmental changes. We integrate ecological community metadata of 7,694 sampling sites for multiple or ganism groups in a machine learning model framework to map the research probability across the Brazilian Amazonia, while identifying the region’s vulnerability to environmental change. 15%–18% of the most ne glected areas in ecological research are expected to experience severe climate or land use changes by 2050. This means that unless we take immediate action, we will not be able to establish their current status, much less monitor how it is changing and what is being lostinfo:eu-repo/semantics/publishedVersio

Pervasive gaps in Amazonian ecological research

Biodiversity loss is one of the main challenges of our time,1,2 and attempts to address it require a clear understanding of how ecological communities respond to environmental change across time and space.3,4 While the increasing availability of global databases on ecological communities has advanced our knowledge of biodiversity sensitivity to environmental changes,5,6,7 vast areas of the tropics remain understudied.8,9,10,11 In the American tropics, Amazonia stands out as the world's most diverse rainforest and the primary source of Neotropical biodiversity,12 but it remains among the least known forests in America and is often underrepresented in biodiversity databases.13,14,15 To worsen this situation, human-induced modifications16,17 may eliminate pieces of the Amazon's biodiversity puzzle before we can use them to understand how ecological communities are responding. To increase generalization and applicability of biodiversity knowledge,18,19 it is thus crucial to reduce biases in ecological research, particularly in regions projected to face the most pronounced environmental changes. We integrate ecological community metadata of 7,694 sampling sites for multiple organism groups in a machine learning model framework to map the research probability across the Brazilian Amazonia, while identifying the region's vulnerability to environmental change. 15%–18% of the most neglected areas in ecological research are expected to experience severe climate or land use changes by 2050. This means that unless we take immediate action, we will not be able to establish their current status, much less monitor how it is changing and what is being lost

CUTE Mote, a customizable and trustable end-device for the Internet of things

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks' architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing- and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices.FCT - Fundação para a Ciência e a Tecnologia (POCI-01-0145-FEDER-007043)info:eu-repo/semantics/publishedVersio

Towards an FPGA-based network layer filter for the Internet of things edge devices

In the near future, billions of new smart devices will connect the big network of the Internet of Things, playing an important key role in our daily life. Allowing IPv6 on the low-power resource constrained devices will lead research to focus on novel approaches that aim to improve the efficiency, security and performance of the 6LoWPAN adaptation layer. This work in progress paper proposes a hardware-based Network Packet Filtering (NPF) and an IPv6 Link-local address calculator which is able to filter the received IPv6 packets, offering nearly 18% overhead reduction. The goal is to obtain a System-on-Chip implementation that can be deployed in future IEEE 802.15.4 radio modules.Tiago Gomes is supported by FCT - Fundação para a Ciência e Tecnologia (grant SFRH/BD/90162/2012). This work has been supported by FCT - Fundação para a Ciência e Tecnologia within the Project Scope: PEst-UID/CEC/00319/2013.info:eu-repo/semantics/publishedVersio

Non-intrusive hardware acceleration for dynamic binary translation in embedded systems

This article describes a non-intrusive hardware acceleration approach for Dynamic Binary Translation (DBT) in modern resource-constrained embedded systems, detailing its motivation, design decisions and overall architecture. It was deployed and tested on DBTOR, an in-house DBT system that targets constrained embedded systems. The performed evaluations demonstrate the feasibility of the proposed method in handling condition code (CC) flags, peripheral remapping and interrupt support, by running legacy MCS-51 code on a modern Arm v7-M architecture (Cortex-M3) that resorts field-programmable gate array (FPGA) technology for acceleration purposes.This work has been supported by FCT - Fundação para a Ciência e Tecnologia within the Project Scope: UID/CEC/00319/2019