Concurrent Algebras for VLSI Design

As the size and complexity of VLSI chips increases, designers are beginning to rely more and more on automated chip design systems to help layout, route, or even design circuits. silicon compilers convert the functional description of a system to a mask level design of a chip that implements the system. In order to ease the task of describing the system, and to help analyse and verify its working, the description languages are based on algebraic systems. A typical circuit has a number of actions occurring at any given time. So we use concurrent algebras as the basis for the description languages. In this paper, we survey algebras that enable the description and analysis of concurrent systems. We examine them particularly from the point of view of using them to implement systems in VLSI. We therefore concentrate on the basics of each algebra, and omit features that are not readily implementable, such as recursion. We will look at four algebras: trace theory, path expressions, Milner's calculus of communicating systems (CCS), and an algebra of finite events (CAFE). We choose the first three since each has been used in some form of silicon compiler or other automated hardware design s)"Item, and together they demonstrate all the features found in higher level description systems for hardware. The fourth is an algebra that we are developing to address the problems of describing systems of events of finite duration. In chapter 2 we introduce an informal net notation and the concept of observers, which we use in the next four chapters to describe each algebra briefly. In chapter 7, we compare the algebras in terms of their treatment of independence, the type of parallel composition they use, and the inter-event dependencies they allow. We end by explaining the relative advantages and disadvantages of the algebras in various situations. The goal hoped that this comparative discussion of the algebras is to aid in the design of process description languages to be used in silicon compilers

Concurrent Algebras for VLSI Design

As the size and complexity of VLSI chips increases, designers are beginning to rely more and more on automated chip design systems to help layout, route, or even design circuits. silicon compilers convert the functional description of a system to a mask level design of a chip that implements the system. In order to ease the task of describing the system, and to help analyse and verify its working, the description languages are based on algebraic systems. A typical circuit has a number of actions occurring at any given time. So we use concurrent algebras as the basis for the description languages. In this paper, we survey algebras that enable the description and analysis of concurrent systems. We examine them particularly from the point of view of using them to implement systems in VLSI. We therefore concentrate on the basics of each algebra, and omit features that are not readily implementable, such as recursion. We will look at four algebras: trace theory, path expressions, Milner's calculus of communicating systems (CCS), and an algebra of finite events (CAFE). We choose the first three since each has been used in some form of silicon compiler or other automated hardware design s)"Item, and together they demonstrate all the features found in higher level description systems for hardware. The fourth is an algebra that we are developing to address the problems of describing systems of events of finite duration. In chapter 2 we introduce an informal net notation and the concept of observers, which we use in the next four chapters to describe each algebra briefly. In chapter 7, we compare the algebras in terms of their treatment of independence, the type of parallel composition they use, and the inter-event dependencies they allow. We end by explaining the relative advantages and disadvantages of the algebras in various situations. The goal hoped that this comparative discussion of the algebras is to aid in the design of process description languages to be used in silicon compilers

Miss Manners: A Specialized Silicon Compiler for Synchronizers

Miss Manners is a synchronizer generator that will produce the layout of a synchronizer given a high-level description. A synchronizer generator is a type of specialized silicon compiler. Synchronizer generators can greatly aid the design of systems that are structured as loosely-coupled networks of autonomous subsystems. Chips that are structured in this way have reduced communication requirements and greater tolerance for transient failures. We describe a language for specifying synchronization requirements and a compiler for translating the language into circuits that enforce the specifications

Modeling Regular and Safe Concurrent Processes (Technical Summary)

The authors have previously described the use of data path expressions and predecessor automata in debugging concurrent systems. In this paper we examine the relationship of these models to two traditional models of concurrent processes: pomset languages and k-safe Petri net systems. We explore the regularity and safety of the concurrent languages described by each of the four models. Our main result is the equivalence of regular safe pomset languages and the languages described by safe data path expressions, safe predecessor automata and k-safe Petri net systems

Psi: A Silicon Compiler for Very Fast Protocol Processing

Conventional protocols implementations typically fall short, by a few orders of magnitude, of supporting the speeds afforded by high-speed optical transmission media. This protocol processing bottleneck is a key hurdle in taking advantage of the opportunities presented by high-speed communications. This paper describes PSi, a silicon compiler that transforms formal protocol specifications into efficient VLSI implementations. PSi takes advantage of the parallelisms intrinsic to a given protocol to accomplish very high-speed implementations. Initial application of PSi to the IEEE 802.2 (logical link control) leads to processing rates in the order of 106 packets per second (p/s). The 802.2 was selected as a benchmark of complexity; light-weight protocols can accomplish even higher processing rates, reaching the limits set by chip clock rates (i.e., a packet per cycle). These speeds significantly exceed typical of software implementations (up to a few hundred p/s) or special hardware-assisted implementations (up to a few thousands p/s). More importantly, at these rates when the packet size is 103-4 bits the protocol throughput of 109-10 bits/sec reaches the limiting throughput afforded by memory technology. Thus, the protocol processing bottleneck is pushed to the ultimate bounds set by VLSI technologies

Seed yield and quality as influenced by growing conditions in hybrid seed production of bitter gourd (Momordica charantia L.) cv. Pusa Hybrid-1

The present investigation was carried out under insect proof net house (IPN) and open field condition (OFC) at Centre for Protected Cultivation Technology and Seed Testing Laboratory of Division of Seed Science &Technology, IARI, New Delhi in bitter gourd cv. Pusa Hybrid-1 during summer season because under open field condition the seed yield and seed quality of bitter gourd drastically reduced due to viral diseases and fruit fly in kharif and early onset of high temperature, unseasonal rains during summer, which restricts the hybrid seed production of bitter gourd under north Indian condition. The observations on seed yield & quality characters and physical properties of seed were recorded. The quality attributes were evaluated immediately after harvest and after 8 months of ambient storage and their results were compared. The experimental results revealed that total number of seed per fruit (46.7), number of filled seed per fruit (45.3), seed yield per fruit (9.41g), seed yield per plant (27.28g), and seed yield per hectare (232kg) were significantly higher under IPN in comparison to OFC. Among the physical parameters of seed, seed width (0.81cm) & seed coat (0.79g) weight recorded significantly higher in IPN. The seed quality attributes immediately after harvest was also significantly superior under IPN compared to OFC except for germination %. The hybrid seed produced under IPN conditions could maintain their superiority for quality traits even after 8 monthsof its ambient storage. The seed yield and seed quality attributes were comparatively superior under IPN conditions. The seed crop grown under IPN overcomes the threat of insect vectors, viral diseases and unfavourable climatic conditions and helps in attaining the better seed yield and quality

Efficacy and safety of triple drug fixed-dose combination of telmisartan, amlodipine and hydrochlorothiazide in the management of hypertension

Background: High blood pressure (BP) is the most prevalent chronic disease in India and its prevalence is rapidly increasing among urban and rural populations. This study was conducted to assess the efficacy and safety of triple drug fixed dose combination of Telmisartan 40 mg, Amlodipine 5 mg and Hydrochlorothiazide 12.5mg. Methods: 30 hypertensive patients having systolic blood pressure ≥ 160 mmHg and diastolic blood pressure ≥ 100 mmHg who were uncontrolled on dual drug therapy with Telmisartan-Amlodipine or Telmisartan-Hydrochlorothiazide combinations were enrolled in this study. The treatment period was of 120 days and patients were administered once daily fixed dose combination of Telmisartan 40 mg, Amlodipine 5 mg and Hydrochlorothiazide 12.5 mg. Patients were evaluated on 30th, 60th and 120th days of treatment. Results: There was statistically significant (p<0.0001) decrease in systolic blood pressure from baseline to 30th, 60th and 120th day of treatment mean±SD (157.0±8.68 mmHg vs 148.7±8.19, 137.3±7.84, and 127.0±7.02 mmHg) respectively. Similarly the diastolic blood pressure (DBP) was significantly (p<0.0001) reduced from the baseline to the 30th, 60th and 120th day of treatment (100.0±6.43 mmHg vs. 96.0±6.21, 86.6±6.06 and 80.6±2.53 mmHg respectively). Conclusion: Thus triple drug fixed dose combination of Telmisartan, Amlodipine and hydrochlorothiazide was found to be effective and safe option for the optimal management of hypertension.

The GALNT9, BNC1 and CCDC8 genes are frequently epigenetically dysregulated in breast tumours that metastasise to the brain.

Tumour metastasis to the brain is a common and deadly development in certain cancers; 18-30 % of breast tumours metastasise to the brain. The contribution that gene silencing through epigenetic mechanisms plays in these metastatic tumours is not well understood

Effect of truss retention and pruning of berry on seed yield and quality of cherry tomato (Solanum lycopersicum var cerasiforme) grown under different polyhouse structures

Study was conducted to evaluate the effect of retention of truss per plant and pruning of berries per truss on seed yield and quality of cherry tomato (Solanum tycopersicum var cerasiforme L.) grown under three different polyhouse structures, viz. semi climate controlled polyhouse (P1), naturally ventilated polyhouse (P2) and insect proof nethouse (P3). Among the structures P1 gave higher berry weight (7.67 g), number of seeds/berry (60.66), 100 seed weight (0.1328 g), seed yield/berry (0.0912 g), germination (84.90%), vigour index-I (650.64), vigour index-II (1.47) and lower EC (0.0086 µS/g/cm), when compared to P2 and P3. The retention of 5 truss per plant (V1) recorded higher berry weight (7.37 g), number of seeds/berry (63.25), 100 seed weight (0.1319 g), seed yield/berry (0.0886 g), germination (84.68 %), vigour index-I (640.97), vigour index-II (1.43) and lower electrical conductivity (0.0083 µS/ g/cm), as compared to V2 and V3. The thinning of berry, i.e 10 per truss (B1) has given significantly higher mean berry weight (8.21 g), number of seeds/berry (61.53), 100 seed weight (0.1323 g), 100 seed weight (0.1323 g), seed yield/berry (0.0913 g), germination (86.01%), vigour index-I (651.96), vigour-II (1.46) and lower EC (0.0080 µS/g/ cm) in comparison to B2 and B3