Despliegue de clusters GPU de bajo coste

En la actualidad, la demanda de procesamiento se incrementa cada día. La sociedad genera una cantidad monstruosa de datos al día y la necesidad de poder procesar todos ellos nos lleva a crear nuevos centros de datos y de computación donde tratarlos. Como parte negativa, estos centros son costosos de crear y todavía más de mantener. Por ello, el objetivo de este Trabajo Final de Grado es el desarrollo y la implementación de un clúster de bajo coste utilizando equipamientos disponibles en centros de enseñanza públicos. Para ello se ha desarrollado un conjunto de software para gestión, instalación y puesta en funcionamiento de un clúster de GPUs de bajo coste así como para su exposición para el uso por parte de un público general poco especializado. Para ello, en este proyecto se ha desarrollado y se implementa una API Full Rest para el lanzamiento de los trabajos dentro de un clúster a través de una interfaz web. Como prueba de concepto, se ha desplegado el sistema propuesto en el laboratorio L14 de la Escuela Politécnica Superior de la Universidad de Alicante. De esta forma, se ha configura un laboratorio híbrido capaz de servir tanto para las clases cotidianas como para computación de altas prestaciones. Para finalizar, se establecieron una serie de directivas para comparar el rendimiento del clúster creado con otras soluciones comerciales que están disponibles en la propia Universidad de Alicante

Space Shuttle: A test vehicle for the reliability of the SkyWater 130nm PDK for future space processors

Recently the ASIC industry experiences a massive change with more and more small and medium businesses entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector – which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs – if we can show that the produced chips have favourable radiation properties. In this paper, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors.This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments”. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033) and the European Community’s Horizon Europe programme under the METASAT project (grant agreement 101082622).Peer ReviewedPostprint (author's final draft

Space shuttle: a test vehicle for the reliability of the SkyWater 130nm PDK using OpenLane and the Google/E-fabless shuttle run for future space systems

The ASIC industry is experiencing a massive change in the recent years with more and more small and medium business entering the custom ASIC development. This trend is fueled by the recent open hardware movement and relevant government and privately funded initiatives. These new developments can open new opportunities in the space sector, which is traditionally characterised by very low volumes and very high non-recurrent (NRE) costs, if we can show that the produced chips have favourable radiation properties. In this ACM SRC entry, we describe the design and tape-out of Space Shuttle, the first test chip for the evaluation of the suitability of the SkyWater 130nm PDK and the OpenLane EDA toolchain using the Google/E-fabless shuttle run for future space processors

Space compression algorithms acceleration on embedded multi-core and GPU platforms

Future space missions will require increased on-board computing power to process and compress massive amounts of data. Consequently, embedded multi-core and GPU platforms are considered, which have been shown beneficial for data processing. However, the acceleration of data compression - an inherently sequential task - has not been explored. In this on-going research paper, we parallelize two space compression standards on both CPUs and GPUs using two candidate embedded GPU platforms for space showing that despite the challenging nature of CCSDS algorithms, their parallelization is possible and can provide significant performance benefits.This work was funded by the Ministerio de Ciencia e Innovacion - Agencia Estatal de Investigacion (PID2019-107255GBC21/AEI/10.13039/501100011033 and IJC-2020-045931-I) and partially supported by the European Space Agency (ESA) through the GPU4S (GPU for Space) activity and the HiPEAC Network of Excellence.Peer ReviewedPostprint (author's final draft

Sources of single event effects in the NVIDIA Xavier SoC family under proton irradiation

In this paper we characterise two embedded GPU devices from the NVIDIA Xavier family System-on-Chip (SoC) using a proton beam. We compare the NVIDIA Xavier NX and Industrial devices, that respectively target commercial and automotive applications. We evaluate the Single-Event Effect (SEE) rate of both modules and their sub-components, both the CPU and GPU, using different power modes, and we try for the first time to identify their exact sources using the on-line testing facilities included in their ARM based system. Our conclusion is that the most sensitive part of the CPU complex of the SoC is the tag array of the various cache structures, while no errors were observed in the GPU, probably because of its fast execution compared to the CPU part of the application during the radiation campaign.This work was supported by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) project. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033) and the HiPEAC Network of Excellence.Peer ReviewedPostprint (author's final draft

Functional and timing implications of transient faults in critical systems

Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.This work has been partially funded by ANR-FASY (ANR-21-CE25-0008-01) and received funding by ESA through the 4000136514/21/NL/GLC/my co-funded PhD activity ”Mixed Software/Hardware-based Fault-tolerance Techniques for Complex COTS System-on-Chip in Radiation Environments” and the GPU4S (GPU for Space) project. Moreover, it was partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB-C21 and IJC2020-045931-I (Spanish State Research Agency / http://dx.doi.org/10.13039/501100011033), by the European Union’s Horizon 2020 grant agreement No 739551 (KIOS CoE) and from the Government of the Republic of Cyprus through the Cyprus Deputy Ministry of Research, Innovation and Digital Policy.Peer ReviewedPostprint (author's final draft

Despliegue de clusters GPU de bajo coste

En la actualidad, la demanda de procesamiento se incrementa cada día. La sociedad genera una cantidad monstruosa de datos al día y la necesidad de poder procesar todos ellos nos lleva a crear nuevos centros de datos y de computación donde tratarlos. Como parte negativa, estos centros son costosos de crear y todavía más de mantener. Por ello, el objetivo de este Trabajo Final de Grado es el desarrollo y la implementación de un clúster de bajo coste utilizando equipamientos disponibles en centros de enseñanza públicos. Para ello se ha desarrollado un conjunto de software para gestión, instalación y puesta en funcionamiento de un clúster de GPUs de bajo coste así como para su exposición para el uso por parte de un público general poco especializado. Para ello, en este proyecto se ha desarrollado y se implementa una API Full Rest para el lanzamiento de los trabajos dentro de un clúster a través de una interfaz web. Como prueba de concepto, se ha desplegado el sistema propuesto en el laboratorio L14 de la Escuela Politécnica Superior de la Universidad de Alicante. De esta forma, se ha configura un laboratorio híbrido capaz de servir tanto para las clases cotidianas como para computación de altas prestaciones. Para finalizar, se establecieron una serie de directivas para comparar el rendimiento del clúster creado con otras soluciones comerciales que están disponibles en la propia Universidad de Alicante

GPU4S: Major project outcomes, lessons learnt and way forward

Embedded GPUs have been identified from both private and government space agencies as promising hardware technologies to satisfy the increased needs of payload processing. The GPU4S (GPU for Space) project funded from the European Space Agency (ESA) has explored in detail the feasibility and the benefit of using them for space workloads. Currently at the closing phases of the project, in this paper we describe the main project outcomes and explain the lessons we learnt. In addition, we provide some guidelines for the next steps towards their adoption in space.This work is funded by ESA under the GPU4S (GPU for Space) project (ITT AO/1-9010/17/NL/AF). It is also partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grants PID2019-107255GB and FJCI-2017-34095 and HiPEAC.Peer ReviewedPostprint (author's final draft

The UP2DATE baseline research platforms

The UP2DATE H2020 project focuses on highperformance heterogeneous embedded platforms for critical systems. We will develop observability and controllability solutions to support online updates while ensuring safety and security for mixed-criticality tasks. In this paper, we describe the rationale behind the selection of the baseline research platforms which will be used to develop and demonstrate the project concepts, including a performance comparison to identify the most efficient one.This work is funded by the European Commission’s Horizon 2020 programme under the UP2DATE project (grant agreement 871465). It is also partially supported by the Spanish Ministry of Economy and Competitiveness under grants PID2019-107255GB and FJCI-2017-34095 and HiPEAC.Peer ReviewedPostprint (author's final draft