Differences in Brain Function and Changes with Intervention in Children with Poor Spelling and Reading Abilities

Previous fMRI studies in English-speaking samples suggested that specific interventions may alter brain function in language-relevant networks in children with reading and spelling difficulties, but this research strongly focused on reading impaired individuals. Only few studies so far investigated characteristics of brain activation associated with poor spelling ability and whether a specific spelling intervention may also be associated with distinct changes in brain activity patterns. We here investigated such effects of a morpheme-based spelling intervention on brain function in 20 children with comparatively poor spelling and reading abilities using repeated fMRI. Relative to 10 matched controls, children with comparatively poor spelling and reading abilities showed increased activation in frontal medial and right hemispheric regions and decreased activation in left occipito-temporal regions prior to the intervention, during processing of a lexical decision task. After five weeks of intervention, spelling and reading comprehension significantly improved in the training group, along with increased activation in the left temporal, parahippocampal and hippocampal regions. Conversely, the waiting group showed increases in right posterior regions. Our findings could indicate an increased left temporal activation associated with the recollection of the new learnt morpheme-based strategy related to successful training

On the Physical Design of PRAMs

The Saarbrucken Parallel Random Access Machine (SB-PRAM) is a scalable shared memory machine. At the gate level it is a re-engineered version of the Fluent machine [A. G. Ranade, S. N. Bhatt and S. L. Johnson. The Fluent Abstract Machine. In Proc. 5th MIT Conference on Advanced Research in VLSI, pp. 71--93 (1988)]. It uses hashing of adresses, combining and latency hiding. A prototype with 128 processors is presently being designed. In this paper we deal with several problems related to the physical design of this machine such as the total number of network chips, the geometrical arrangement of boards in the network and the VLSI realization of certain sorting arrays. We also present an extremely fast method to rehash addresses without use of external memory. Research was partially supported by DFG (SFB 124) and SIEMENS AG. A preliminary version of this paper appeared in [1]. 1 Introduction Parallel machines are nowadays classified as multi-computers and multi-processors. In multi-..