High-speed completion detection for current sensing on-chip interconnects

A novel completion detection technique for delay insensitive current sensing on-chip interconnects is presented. The scheme is based on sensing currents on the data wires and comparing the sum of these currents to an appropriately set reference. The goal is to solve the performance bottleneck caused by conventional voltage-mode detection methods. With the channel width of 64 bits, the proposed method is 4.65 times faster and takes 36% less area than the voltage-mode scheme. Furthermore, its speed does not degrade when increasing the channel bit width. It is implemented in a 65 nm CMOS technology

Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems

High-performance fault simulation is one of the essential and preliminary tasks in the process of online and offline testing of machine learning (ML) hardware. Deep neural networks (DNN), as one of the essential parts of ML programs, are widely used in many critical and non-critical applications in Systems-on-Chip and ASIC designs. Through fault simulation for DNNs, by increasing the number of neurons, the fault simulation time increases exponentially. However, the software architecture of neural networks and the lack of dependency between neurons in each inference layer provide significant opportunity for parallelism of the fault simulation time in a multi-processor platform. In this paper, a multi-thread technique for hierarchical fault simulation of neural network is proposed, targeting both permanent and transient faults. During the process of fault simulation the neurons for each inference layer will be distributed among the executing threads. Since in the process of hierarchical fault simulation, the faulty neuron demands proportionally enormous computation comparing to behavioural model of non-faulty neurons, the faulty neuron will be assigned to one thread while the rest of the neurons will be divided among the remaining threads. Experimental results confirm the time efficiency of the proposed fault simulation technique on multi-processor architectures

Unmanned Aerial Vehicles (UAVs): Collision Avoidance Systems and Approaches

Moving towards autonomy, unmanned vehicles rely heavily on state-of-the-art collision avoidance systems (CAS). A lot of work is being done to make the CAS as safe and reliable as possible, necessitating a comparative study of the recent work in this important area. The paper provides a comprehensive review of collision avoidance strategies used for unmanned vehicles, with the main emphasis on unmanned aerial vehicles (UAV). It is an in-depth survey of different collision avoidance techniques that are categorically explained along with a comparative analysis of the considered approaches w.r.t. different scenarios and technical aspects. This also includes a discussion on the use of different types of sensors for collision avoidance in the context of UAVs

Energy-Efficient Formation Morphing for Collision Avoidance in a Swarm of Drones

Two important aspects in dealing with autonomous navigation of a swarm of drones are collision avoidance mechanism and formation control strategy; a possible competition between these two modes of operation may have negative implications for success and efficiency of the mission. This issue is exacerbated in the case of distributed formation control in leader-follower based swarms of drones since nodes concurrently decide and act through individual observation of neighbouring nodes' states and actions. To dynamically handle this duality of control, a plan of action for multi-priority control is required. In this paper, we propose a method for formation-collision co-awareness by adapting the thin-plate splines algorithm to minimize deformation of the swarm's formation while avoiding obstacles. Furthermore, we use a non-rigid mapping function to reduce the lag caused by such maneuvers. Simulation results show that the proposed methodology maintains the desired formation very closely in the presence of obstacles, while the response time and overall energy efficiency of the swarm is significantly improved in comparison with the existing methods where collision avoidance and formation control are only loosely coupled. Another important result of using non-rigid mapping is that the slowing down effect of obstacles on the overall speed of the swarm is significantly reduced, making our approach especially suitable for time critical missions

FORESAIL-1 cubesat mission to measure radiation belt losses and demonstrate de-orbiting

Abstract Today, the near-Earth space is facing a paradigm change as the number of new spacecraft is literally sky-rocketing. Increasing numbers of small satellites threaten the sustainable use of space, as without removal, space debris will eventually make certain critical orbits unusable. A central factor affecting small spacecraft health and leading to debris is the radiation environment, which is unpredictable due to an incomplete understanding of the near-Earth radiation environment itself and its variability driven by the solar wind and outer magnetosphere. This paper presents the FORESAIL-1 nanosatellite mission, having two scientific and one technological objectives. The first scientific objective is to measure the energy and flux of energetic particle loss to the atmosphere with a representative energy and pitch angle resolution over a wide range of magnetic local times. To pave the way to novel model - in situ data comparisons, we also show preliminary results on precipitating electron fluxes obtained with the new global hybrid-Vlasov simulation Vlasiator. The second scientific objective of the FORESAIL-1 mission is to measure energetic neutral atoms (ENAs) of solar origin. The solar ENA flux has the potential to contribute importantly to the knowledge of solar eruption energy budget estimations. The technological objective is to demonstrate a satellite de-orbiting technology, and for the first time, make an orbit manoeuvre with a propellantless nanosatellite. FORESAIL-1 will demonstrate the potential for nanosatellites to make important scientific contributions as well as promote the sustainable utilisation of space by using a cost-efficient de-orbiting technology.Peer reviewe

2005 International Symposium on System-on-Chip: Proceedings

this paper presents two asynchronous links between any two independently clocked synchronous modules. The first link is based on using synchronizers and synchronous and asynchronous FIFOs which compensates the increase of latency due to synchronization. Due to this the latency of this link is reduced to 2.08nsee. The mean time between failures of this link is 35 years, which is more than enough for any design. The second link generates clock for each module locally and stops it whenever there is communication between module and link. In this link there is no synchronization failure at all. The latency and power consumption of both links are very small which makes them efficient links for SoC. Since the two link architectures let the use of different clocks in each synchronous module, it makes the system modular and enables easy reusage of different synchronous modules in the system. The circuits are simulated using the analog environment of Spectre with 0.13um technology

Proceedings: IEEE Computer Society Annual Sysmposium on VLSI 2006: Emerging VLSI Technologies and Architectures

In this paper we present the circuit implementation of a new asynchronous delay-insensitive on-chip link structure, where two modules placed on the opposite sides of the link can exchange data simultaneously. Unlike the conventional delay-insensitive dual-rail link which requires 2N + 1 interconnects to transfer N-data bit, N + 1 interconnects are required in this design. As two transceivers can access simultaneously the same physical interconnect the number of required interconnects halves compared to bidirectional transfer based on two separate unidirectional dual-rail links. This makes the link cost effective for future SoC The transceiver circuits are designed using multiple-valued current-mode logic, linear summation is implemented by wiring without active devices simplifying the resulting circuitry. By using 110 mV voltage swing the power consumption of the link is 8.32 mW for 689ps propagation delay and 5mm interconnect length. Some of the potential application areas of this link are between locally clocked modules in GALS system, between routers of NoC nodes, and in adaptive and reeonfigurable system where feedback information is crucial. The circuit is designed and simulated using Cadence Analog Spectre with 0.13 mu m CMOS technology

Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip

Dynamic Reliability Management (DRM) is a common approach to mitigate aging and wear-out effects in multi- /many-core systems. State-of-the-art DRM approaches apply finegrained control on resource management to increase/balance the chip reliability while considering other system constraints, e.g., performance, and power budget. Such approaches, acting on various knobs such as workload mapping and scheduling, Dynamic Voltage/Frequency Scaling (DVFS) and Per-Core Power Gating (PCPG), demonstrated to work properly with the various aging mechanisms, such as electromigration, and Negative-Bias Temperature Instability (NBTI). However, we claim that they do not suffice for thermal cycling. Thus, we here propose a novel thermal-cycling-aware DRM approach for shared-memory many-core systems running multi-threaded applications. The approach applies a fine-grained control capable at reducing both temperature levels and variations. The experimental evaluations demonstrated that the proposed approach is able to achieve 39% longer lifetime than past approaches