Evaluation of appendicitis risk prediction models in adults with suspected appendicitis

Background Appendicitis is the most common general surgical emergency worldwide, but its diagnosis remains challenging. The aim of this study was to determine whether existing risk prediction models can reliably identify patients presenting to hospital in the UK with acute right iliac fossa (RIF) pain who are at low risk of appendicitis. Methods A systematic search was completed to identify all existing appendicitis risk prediction models. Models were validated using UK data from an international prospective cohort study that captured consecutive patients aged 16–45 years presenting to hospital with acute RIF in March to June 2017. The main outcome was best achievable model specificity (proportion of patients who did not have appendicitis correctly classified as low risk) whilst maintaining a failure rate below 5 per cent (proportion of patients identified as low risk who actually had appendicitis). Results Some 5345 patients across 154 UK hospitals were identified, of which two‐thirds (3613 of 5345, 67·6 per cent) were women. Women were more than twice as likely to undergo surgery with removal of a histologically normal appendix (272 of 964, 28·2 per cent) than men (120 of 993, 12·1 per cent) (relative risk 2·33, 95 per cent c.i. 1·92 to 2·84; P < 0·001). Of 15 validated risk prediction models, the Adult Appendicitis Score performed best (cut‐off score 8 or less, specificity 63·1 per cent, failure rate 3·7 per cent). The Appendicitis Inflammatory Response Score performed best for men (cut‐off score 2 or less, specificity 24·7 per cent, failure rate 2·4 per cent). Conclusion Women in the UK had a disproportionate risk of admission without surgical intervention and had high rates of normal appendicectomy. Risk prediction models to support shared decision‐making by identifying adults in the UK at low risk of appendicitis were identified

A novel processor architecture with a hardware microkernel to improve the performance of task-based systems

The use of hardware to perform part of central processing unit (CPU) processing functions is a consolidated practice that produces good results in terms of power and performance when applied in embedded systems. This letter describes the changes in the processor architecture to embed the functions of a microkernel to boost the performance of task-based systems. Part of the CPU overhead is caused by the microkernel to run the scheduler algorithm and context switching. Therefore, the microkernel's functions, supported by a single additional internal register bank, were implemented by hardware to work in parallel with the CPU to reduce the task dispatch time. The experimental results show that by using this approach, the performance is virtually independent of the time slice, whereas the conventional approach (software implementation) is degraded by 79% as the time slice decreases1121574649CONSELHO NACIONAL DE DESENVOLVIMENTO CIENTÍFICO E TECNOLÓGICO - CNPQCOORDENAÇÃO DE APERFEIÇOAMENTO DE PESSOAL DE NÍVEL SUPERIOR - CAPESFUNDAÇÃO DE AMPARO À PESQUISA DO ESTADO DE SÃO PAULO - FAPESPnão temnão tem308702/2016-

Using diamond layout style to boost MOSFET frequency response of analogue IC

A way to improve the metal–oxide–semiconductor field effect transistor (MOSFET) analogue electrical performance, still little explored, is to modify their aspect form or ratio (AR) by the use of innovative layout styles. The diamond MOSFET (DM) is an example of this approach. It presents hexagonal gate geometry. This new layout structure for MOSFET induces two additional effects in comparison with the conventional (i.e. rectangular gate geometry) MOSFET (CM) counterpart, which improves the device’s electrical performance: the longitudinal corner effect (LCE) and parallel association of MOSFET with different channel length effect (PAMDLE). How the diamond layout style (DLS) can significantly enhance the device’s frequency response (FR) by using two different integrated circuits’ (IC) complementary metal–oxide–semiconductor (CMOS) manufacturing process technologies (bulk and silicon-on-insulator (SOI)) is demonstrated

Boosting the MOSFETs matching by using diamond layout style

This paper performs an experimental comparative study of the Metal-Oxide-Semiconductor Silicon-On-Insulator (SOI) Field Effect Transistors (MOSFETs) matching, which are implemented with the hexagonal gate geometry (Diamond) and classical rectangular one. Some of the main analog parameters of 360 devices are investigated. The results demonstrate that the Diamond SOI MOSFETs with α angles equal to 53.1° and 90° are capable of boosting in more than 20% the devices matching in comparison to those observed in the typical rectangular SOI MOSFETs, regarding the same gate area and bias conditions. Therefore, the Diamond layout style is an alternative technique to reduce the MOSFETs' mismatching regarding the analog SOI CMOS ICs applications

Diamond layout style impact on SOI MOSFET in high temperature environment

This work performs an experimental comparative study between the Diamond (hexagonal gate geometry) and Standard layouts styles for Metal–Oxide–Semiconductor Field Effect Transistor in high temperatures environment. The devices were manufactured with the 1 lm Silicon-on-Insulator CMOS technology. The results demonstrate that the Diamond SOI MOSFET is capable to keep active the Longitudinal Corner Effect and the Parallel Association of MOSFET with Different Channel Lengths Effect in high temperature conditions and consequently to continue presenting a better electrical performance than the one found in the conventional SOI MOSFET

Performance of OCTO Layout Style on SOI MOSFET Switches under High-temperature Operation

The present paper performs an experimental comparative study of the main switching electrical parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named Octo SOI MOSFET (OSM), in comparison with the typical rectangular one, regarding a large range of temperature, varying from 300 K to 573 K. The devices were manufactured in a 2 μm fully-depleted SOI (CMOS) technology and are n-type. The results have shown that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE), which are intrinsic effects of the gate octagonal structure of the MOSFET. Besides, it is able to present a higher electrical performance as compared to its rectangular SOI MOSFET (RSM) counterpart (same channel width and bias conditions). As an illustration, the OSM on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller as compared to those found in its RSM counterpart

Compact diamond MOSFET model accounting for PAMDLE applicable down 150nm node

The performance improvements for integrated circuit applications of silicon-on-insulator (SOI) metal–oxide semiconductor field-effect transistors (MOSFETs) implemented with diamond layout style (hexagonal gate geometry) are quantified, thanks to the longitudinal corner effect and parallel association of MOSFETs with different channel lengths effect contributions. Futhermore, an accurate analytical drain current model for planar diamond SOI MOSFET for micrometre scale effective channel lengths is proposed and validated. The concept is then extended by 3D simulations for the 150 nm node fully-depleted SOI n-channel MOSFETs

Potential Of Improved Gain In Operational Transconductance Amplifier Using 0.5 µm Graded-Channel SOI NMOSFETs For Applications In The Gigahertz Range

This paper studies the potential of improved voltage gain CMOS Operational Transconductance Amplifiers (OTAs) implemented with Graded-Channel (GC) SOI nMOSFETs for applications in the gigahertz range at room temperature using 0.5 μ.m long transistors. Two different design targets were taken in account, regarding similar transconductance over drain current ratio, power dissipation and die area. Comparisons with OTAs made with conventional SOI nMOSFETs are performed showing that the GC OTAs present larger open-loop voltage gain without degrading unit voltage gain frequency and phase margin. SPICE simulations are used to demonstrate the analysis