Estudo de Parâmetros Analógicos de Transistores SOI MOSFET de Canal Gradual Submicrométricos

O desempenho de transistores SOI de canal gradual (GC) em aplicações analógicas está profundamente relacionado ao desenvolvimento da tecnologia na área da microeletrônica. Superar este desafio requer aperfeiçoar o conhecimento dos parâmetros que caracterizam o dispositivo e confirmar se seu desempenho permanece superior aos transistores uniformemente dopados. O presente estudo traz uma comparação entre transistores SOI submicrométricos convencionais (uniformemente dopados) e GC SOI nMOSFETs com diferentes comprimentos de canal e razão LLD/L. A tensão de limiar, inclinação de sublimiar, máxima transcondutância, condutância de saída, ganho intrínseco de tensão e freqüência de ganho unitário foram usados para esta análise

Relação entre qualidade de vida e prevalencia de ideação suicida em pacientes atendidos no programa de transtorno de humor : HCPA

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EFFECT OF THE DISTRIBUTION OF STATES IN AMORPHOUS IN-GA-ZN-O LAYERS ON THE CONDUCTION MECHANISM OF THIN FILM TRANSISTORS ON ITS BASE

Amorphous In-Ga-Zn-O Thin Film Transistors (a-IGZO TFTs) have proven to be an excellent approach for flat panel display drivers using organic light emitting diodes, due to their high mobility and stability compared to other types of TFTs. These characteristics are related to the specifics of the metal-oxygen-metal bonds, which give raise to spatially distributed s orbitals that can overlap between them. The magnitude of the overlap between s orbitals seems to be little sensitive to the presence of the distorted bonds, allowing high values of mobility, even in devices fabricated at room temperature. In this paper, we show the effect of the distribution of states in the a-IGZO layer on the main conduction mechanism of the a-IGZO TFTs, analyzing the behavior with temperature of the drain current.

FOSS EKV2.6 Verilog-A Compact MOSFET Model

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice

Analog circuit design using graded-channel silicon-on-insulator nMOSFETs

An extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) MOSFETs in comparison to conventional fully depleted (1713) transistors is performed. Performances of single-transistor operational transconductance amplifier (OTA) implemented using GC and conventional FD SOI nMOSFETs are compared. Improvements of the DC gain and unity-gain frequency resulting from the extremely reduced output conductance and the increased transconductance in the GC devices are discussed, based on experimental results, establishing design guidelines in order to aim at GC micropower or wide bandwidth OTAs. Two-dimensional simulations are used to analyze the intrinsic-gate capacitances in linear and saturation regions, establishing that GC transistors present almost the same capacitive amount than the conventional FD transistors in a typical analog range of operation. Current mirrors fabricated using GC and conventional MOSFETs are compared. It is demonstrated that GC MOSFETs can provide high precision current mirrors with enhanced output swing. (C) 2002 Elsevier Science Ltd. All rights reserved

Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures

This work studies the operation of source-follower buffers implemented with standard and graded-channel (GC) fully depleted (FD) SCI nMOSFETs at low temperatures. The analysis is performed by comparing the voltage gain of buffers implemented with GC and standard SOI nMOS transistors considering devices with the same mask channel length and same effective channel length. It is shown that the use of GC devices allows for achieving improved gain in all inversion levels in a wide range of temperatures. In addition, this improvement increases as temperature is reduced. It is shown that GC transistors can provide virtually constant gain, while for standard devices, the gain departs from the maximum value depending on the temperature and inversion level imposed by the bias current and input voltage. Two-dimensional numerical simulations were performed in order to study the reasons for the enhanced gain of GC MOSFETs at low temperatures. (C) 2009 Elsevier Ltd. All rights reserved