Improved multiple faults-aware placement strategy: Reducing the overheads and error rates in digital circuits

State-of-the-art commercial placement tools have as goals to optimize area, timing, and power. Over the years, several reliability oriented placement strategies have been proposed with distinct goals, such as to improve the error rate. However, we found that there are still improvements that can be made for this type of approach, to improve not only the error rates but also the performance of the placer itself. Thus, this paper proposes several improvements toward an efficient multiple faults-aware placement strategy. First, an analytical method to profile pair of gates is proposed. Second, we add another level of optimization to reduce the amount of wirelength observed after the placement is completed without jeopardizing the main objective (reliability). Third, we propose a way to manipulate white spaces between gates smartly, to separate the gates that are profiled as the most likely to reduce the error rate when paired adjacently in the circuit. Results show that a wirelength reduction of up to 61% is achieved. Also, additional reduction of the error rate of up to 23% can be achieved with only an overhead on placement execution time

VEasy: um conjunto de ferramentas direcionado aos desafios da verificação funcional

Esta dissertação descreve um conjunto de ferramentas, VEasy, o qual foi desenvolvido especificamente para auxiliar no processo de Verificação Funcional. VEasy contém quatro módulos principais, os quais realizam tarefas-chave do processo de verificação como linting, simulação, coleta/análise de cobertura e a geração de testcases. Cada módulo é comentado em detalhe ao longo dos capítulos. Todos os módulos são integrados e construídos utilizando uma Interface Gráfica. Esta interface possibilita o uso de uma metodologia de criação de testcases estruturados em camadas, onde é possível criar casos de teste complexos através do uso de operações do tipo drag-and-drop. A forma de uso dos módulos é exemplificada utilizando projetos simples escritos em Verilog. As funcionalidades da ferramenta, assim como o seu desempenho, são comparadas com algumas ferramentas comerciais e acadêmicas. Assim, algumas conclusões são apresentadas, mostrando que o tempo de simulação é consideravelmente menor quando efetuada a comparação com as ferramentas comerciais e acadêmicas. Os resultados também mostram que a metodologia é capaz de permitir um alto nível de automação no processo de criação de testcases através do modelo baseado em camadas.This thesis describes a tool suite, VEasy, which was developed specifically for aiding the process of Functional Verification. VEasy contains four main modules that perform linting, simulation, coverage collection/analysis and testcase generation, which are considered key challenges of the process. Each of those modules is commented in details throughout the chapters. All the modules are integrated and built on top of a Graphical User Interface. This framework enables the testcase automation methodology which is based on layers, where one is capable of creating complex test scenarios using drag-anddrop operations. Whenever possible the usage of the modules is exemplified using simple Verilog designs. The capabilities of this tool and its performance were compared with some commercial and academic functional verification tools. Finally, some conclusions are drawn, showing that the overall simulation time is considerably smaller with respect to commercial and academic simulators. The results also show that the methodology is capable of enabling a great deal of testcase automation by using the layering scheme

Méthodes d'analyse et techniques d'amélioration de fiabilité pour les circuits numériques

With the current advances achieved in the manufacturing process of integrated circuits, a series of reliability-threatening mechanisms have emerged or have become more prominent. For instance, physical defects originating from poorly lithographed wires, vias and other low-level devices are commonly seen in nanometric circuits. On the other hand, circuits have also become more sensitive to the strikes of highly energized particles. Both mechanisms, although essentially different, can cause multiple faults that contribute for lower reliabilities in integrated circuits. Multiple faults are more troubling than single faults since these are more severe and also because they can overcome fault tolerance techniques. Digital circuits are used in most electronic systems nowadays, but there is a specific context in which they are required to be reliable. Such context comprises high-dependability applications. This is the scenario in which this thesis is conceived. It’s goals are twofold : (a) to pro pose methods to assess the reliability of digital circuits, and (b) to propose techniques for reliability improvement. Concerning the first goal, several methods have been proposed in the literature and the text shows how these methods present limitations with respect to circuit size (number of gates), circuit type (sequential or combinational) and fault profile (single versus multiple faults). This thesis proposes two methods for reliability assessment. The first method is termed SPR+ and its targeted at the analysis of combinational logic only. SPR+ improves the average analysis accuracy by taking into account the effect of each fanout reconvergent node to the overall circuit reliability. Another method, termed SNaP, is also proposed in this thesis. It is a hybrid approach since it is partially based on simulation. SNaP can be used for combinational and sequential logic and can also be emulated in an FPGA device for faster analysis. Both SPR+ and SNaP can cope with multiple faults.Au cours des dernières années, un développement continu a été observé dans les domaines des systèmes électroniques et des ordinateurs. Une série de mécanismes menaçant la fiabilité ont émergé. Par exemple, des défauts physiques provenant de fils mal lithographié, vias et d'autres dispositifs de bas niveau sont fréquemment observées dans les circuits nanométriques. D'autre part, les circuits sont également devenus plus sensibles aux grèves de particules excitées. Ces deux mécanismes, bien que essentiellement différente, peuvent causer de multiples fautes qui contribuent pour fiabilités plus faibles dans les circuits intégrés. Fautes multiples sont plus inquiétant que de simples car elles sont plus graves et aussi parce qu'ils peuvent surmonter les techniques de tolérance aux fautes. Les circuits numériques sont utilisés dans la plupart des systèmes électroniques aujourd'hui, mais il y a un contexte spécifique dans lequel ils doivent être fiable. Tel contexte comprend des applications de haute dépendabilité. Et cela est le scénario dans lequel cette thèse est conçu. Il a un double objectif: (a) de proposer des méthodes pour évaluer la fiabilité des circuits numériques, et (b) de proposer des techniques d'amélioration de la fiabilité. En ce qui concerne le premier objectif, plusieurs méthodes ont été proposées dans la littérature et le texte montre comment ces méthodes présentent des limitations en ce qui concerne la taille de circuit (nombre de portes), le type de circuit (séquentielle ou combinatoire) et le profil de faute (unique ou fautes multiples). Cette thèse propose deux méthodes pour l'évaluation de la fiabilité. La première méthode est appelée SPR+ et elle vise l'analyse de la logique combinatoire seulement. SPR+ améliore la précision de l'analyse, en tenant compte de l'effet de chaque nœud de fanout par rapport à la fiabilité de l'ensemble du circuit. Une autre méthode, appelée SNaP, est également proposé dans cette thèse. Il s'agit d'une approche hybride, car il est partiellement basée sur la simulation. SNaP peut être utilisé pour la logique combinatoire et séquentielle, et peut également être émulé dans un dispositif FPGA pour une analyse plus rapide. Les deux méthodes, SPR+ et SNAP, peuvent traiter de fautes multiples

Reliability analysis methods and improvement techniques applicable to digital circuits

Au cours des dernières années, un développement continu a été observé dans les domaines des systèmes électroniques et des ordinateurs. Une série de mécanismes menaçant la fiabilité ont émergé. Par exemple, des défauts physiques provenant de fils mal lithographié, vias et d'autres dispositifs de bas niveau sont fréquemment observées dans les circuits nanométriques. D'autre part, les circuits sont également devenus plus sensibles aux grèves de particules excitées. Ces deux mécanismes, bien que essentiellement différente, peuvent causer de multiples fautes qui contribuent pour fiabilités plus faibles dans les circuits intégrés. Fautes multiples sont plus inquiétant que de simples car elles sont plus graves et aussi parce qu'ils peuvent surmonter les techniques de tolérance aux fautes. Les circuits numériques sont utilisés dans la plupart des systèmes électroniques aujourd'hui, mais il y a un contexte spécifique dans lequel ils doivent être fiable. Tel contexte comprend des applications de haute dépendabilité. Et cela est le scénario dans lequel cette thèse est conçu. Il a un double objectif: (a) de proposer des méthodes pour évaluer la fiabilité des circuits numériques, et (b) de proposer des techniques d'amélioration de la fiabilité. En ce qui concerne le premier objectif, plusieurs méthodes ont été proposées dans la littérature et le texte montre comment ces méthodes présentent des limitations en ce qui concerne la taille de circuit (nombre de portes), le type de circuit (séquentielle ou combinatoire) et le profil de faute (unique ou fautes multiples). Cette thèse propose deux méthodes pour l'évaluation de la fiabilité. La première méthode est appelée SPR+ et elle vise l'analyse de la logique combinatoire seulement. SPR+ améliore la précision de l'analyse, en tenant compte de l'effet de chaque nœud de fanout par rapport à la fiabilité de l'ensemble du circuit. Une autre méthode, appelée SNaP, est également proposé dans cette thèse. Il s'agit d'une approche hybride, car il est partiellement basée sur la simulation. SNaP peut être utilisé pour la logique combinatoire et séquentielle, et peut également être émulé dans un dispositif FPGA pour une analyse plus rapide. Les deux méthodes, SPR+ et SNAP, peuvent traiter de fautes multiples.With the current advances achieved in the manufacturing process of integrated circuits, a series of reliability-threatening mechanisms have emerged or have become more prominent. For instance, physical defects originating from poorly lithographed wires, vias and other low-level devices are commonly seen in nanometric circuits. On the other hand, circuits have also become more sensitive to the strikes of highly energized particles. Both mechanisms, although essentially different, can cause multiple faults that contribute for lower reliabilities in integrated circuits. Multiple faults are more troubling than single faults since these are more severe and also because they can overcome fault tolerance techniques. Digital circuits are used in most electronic systems nowadays, but there is a specific context in which they are required to be reliable. Such context comprises high-dependability applications. This is the scenario in which this thesis is conceived. It’s goals are twofold : (a) to pro pose methods to assess the reliability of digital circuits, and (b) to propose techniques for reliability improvement. Concerning the first goal, several methods have been proposed in the literature and the text shows how these methods present limitations with respect to circuit size (number of gates), circuit type (sequential or combinational) and fault profile (single versus multiple faults). This thesis proposes two methods for reliability assessment. The first method is termed SPR+ and its targeted at the analysis of combinational logic only. SPR+ improves the average analysis accuracy by taking into account the effect of each fanout reconvergent node to the overall circuit reliability. Another method, termed SNaP, is also proposed in this thesis. It is a hybrid approach since it is partially based on simulation. SNaP can be used for combinational and sequential logic and can also be emulated in an FPGA device for faster analysis. Both SPR+ and SNaP can cope with multiple faults

Selective Hardening Concerning Single and Multiple Faults

National audienc

Selective Hardening Methodology Concerning Multiple Faults

International audienc

Single Event Transient Mitigation Through Pulse Quenching: Effectiveness at Circuit Level

International audienc

Circuit-level Hardening Against Multiple Faults: Combining Global TMR and Selective Hardening

National audienc

Exploring the limitations of software-based techniques in SEE fault coverage

This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of a MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions may lead designers into developing more efficient techniques to detect these types of faults