Nanoscale resistive switching memory devices: a review

In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I–V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed

Accumulative Polarization Reversal in Nanoscale Ferroelectric Transistors

The electric-field-driven and reversible polarization switching in ferroelectric materials provides a promising approach for nonvolatile information storage. With the advent of ferroelectricity in hafnium oxide, it has become possible to fabricate ultrathin ferroelectric films suitable for nanoscale electronic devices. Among them, ferroelectric field-effect transistors (FeFETs) emerge as attractive memory elements. While the binary switching between the two logic states, accomplished through a single voltage pulse, is mainly being investigated in FeFETs, additional and unusual switching mechanisms remain largely unexplored. In this work, we report the natural property of ferroelectric hafnium oxide, embedded within a nanoscale FeFET, to accumulate electrical excitation, followed by a sudden and complete switching. The accumulation is attributed to the progressive polarization reversal through localized ferroelectric nucleation. The electrical experiments reveal a strong field and time dependence of the phenomenon. These results not only offer novel insights that could prove critical for memory applications but also might inspire to exploit FeFETs for unconventional computing

Multi-staged deposition of trench-gate oxides for power MOSFETs

Here, silicon oxide was formed in a U-shaped trench of a power metal-oxide semiconductor field-effect transistor device by various processes. One SiO₂ formation process was performed in multiple steps to create a low-defect Si-SiO₂ interface, where first a thin initial oxide was grown by thermal oxidation followed by the deposition of a much thicker oxide layer by chemical vapor deposition (CVD). In a second novel approach, silicon nitride CVD was combined with radical oxidation to form silicon oxide in a stepwise sequence. The resulting stack of silicon oxide films was then annealed at temperatures between 1000 and 1100 °C. All processes were executed in an industrial environment using 200 mm-diameter (100)-oriented silicon wafers. The goal was to optimize the trade-off between wafer uniformity and conformality of the trenches. The thickness of the resulting silicon oxide films was determined by ellipsometry of the wafer surface and by scanning electron microscopy of the trench cross sections. The insulation properties such as gate leakage and electrical breakdown were characterized by current–voltage profiling. The electrical breakdown was found to be highest for films treated with rapid thermal processing. The films fabricated via the introduced sequential process exhibited a breakdown behavior comparable to films deposited by the common low-pressure CVD technique, while the leakage current at electric fields higher than 5 MV/cm was significantly lower

SDVSRM - a new SSRM based technique featuring dynamically adjusted, scanner synchronized sample voltages for measurement of actively operated devices

Scanning spreading resistance microscopy (SSRM) with its high spatial resolution and high dynamic signal range is a powerful tool for two-dimensional characterization of semiconductor dopant areas. However, the application of the method is limited to devices in equilibrium condition, as the investigation of actively operated devices would imply potential differences within the device, whereas SSRM relies on a constant voltage difference between sample surface and probe tip. Furthermore, the standard preparation includes short circuiting of all device components, limiting applications to devices in equilibrium condition. In this work scanning dynamic voltage spreading resistance microscopy (SDVSRM), a new SSRM based two pass atomic force microscopy (AFM) technique is introduced, overcoming these limitations. Instead of short circuiting the samples during preparation, wire bond devices are used allowing for active control of the individual device components. SDVSRM consists of two passes. In the first pass the local sample surface voltage dependent on the dc biases applied to the components of the actively driven device is measured as in scanning voltage microscopy (SVM). The local spreading resistance is measured within the second pass, in which the afore obtained local surface voltage is used to dynamically adjust the terminal voltages of the device under test. This is done in a way that the local potential difference across the nano-electrical contact matches the software set SSRM measurement voltage, and at the same time, the internal voltage differences within the device under test are maintained. In this work the proof of the concept could be demonstrated by obtaining spreading resistance data of an actively driven photodiode test device. SDVSRM adds a higher level of flexibility in general to SSRM, as occurring differences in cross section surface voltage are taken into account. These differences are immanent for actively driven devices, but can also be present at standard, short circuited samples. Therefore, SDVSRM could improve the characterization under equilibrium conditions as well

Ferroelectric hafnium oxide for ferroelectric random-access memories and ferroelectric field-effect transistors

Ferroelectrics are promising for nonvolatile memories. However, the difficulty of fabricating ferroelectric layers and integrating them into complementary metal oxide semiconductor (CMOS) devices has hindered rapid scaling. Hafnium oxide is a standard material available in CMOS processes. Ferroelectricity in Si-doped hafnia was first reported in 2011, and this has revived interest in using ferroelectric memories for various applications. Ferroelectric hafnia with matured atomic layer deposition techniques is compatible with three-dimensional capacitors and can solve the scaling limitations in 1-transistor-1-capacitor (1T-1C) ferroelectric random-access memories (FeRAMs). For ferroelectric field-effect-transistors (FeFETs), the low permittivity and high coercive field Ec of hafnia ferroelectrics are beneficial. The much higher Ec of ferroelectric hafnia, however, makes high endurance a challenge. This article summarizes the current status of ferroelectricity in hafnia and explains how major issues of 1T-1C FeRAMs and FeFETs can be solved using this material system

On the stabilization of ferroelectric negative capacitance in nanoscale devices

Recently, the proposal to use voltage amplification from ferroelectric negative capacitance (NC) to reduce the power dissipation in nanoelectronic devices has attracted significant attention. Homogeneous Landau theory predicts, that by connecting a ferroelectric in series with a dielectric capacitor, a hysteresis-free NC state can be stabilized in the ferroelectric below a critical film thickness. However, there is a strong discrepancy between experimental results and the current theory. Here, we present a comprehensive revision of the theory of NC stabilization with respect to scaling of material and device dimensions based on multi-domain Ginzburg–Landau theory. It is shown that the use of a metal layer in between the ferroelectric and the dielectric will inherently destabilize NC due to domain formation. However, even without this metal layer, domain formation can reduce the critical ferroelectric thickness considerably, limiting not only the range of NC stabilization, but also the maximum amplification attainable. To overcome these obstacles, the downscaling of lateral device dimensions is proposed as a way to prevent domain formation and to enhance the voltage amplification due to NC. These insights will be crucial for future NC device design and scaling towards nanoscale dimensions