Using Hybrid Automata for Diagnosis of Hybrid Dynamical Systems

Physical systems can fail. For this reason the problem of identifying and reacting to faults has received a large attention in the control and computer science communities. In this paper we study the fault diagnosis problem and modeling of Hybrid Dynamical Systems (HDS). Generally speaking, HDS is a system mixing continuous and discrete behaviors that cannot be faithfully modeled neither by using formalism with continuous dynamics only nor by a formalism including only discrete dynamics. We use the well known framework of hybrid automata for modeling hybrid systems, because they combine the continous and discretes parts on the same structure. Hybrid automaton is a states-transitions graph, whose dynamic evolution is represented by discretes and continous steps alternations, also, continous evolution happens in the automaton apexes, while discrete evolution is realized by transitions crossing (arcs) of the graph. Their simulation presents many problems mainly the synchronisation between the two models. Stateflow, used to describe the discrete model, is co-ordinated with Matlab, used to describe the continuous model. This article is a description of a case study, which is a two tanks system

A survey on architectures and energy efficiency in Data Center Networks

Data Center Networks (DCNs) are attracting growing interest from both academia and industry to keep pace with the exponential growth in cloud computing and enterprise networks. Modern DCNs are facing two main challenges of scalability and cost-effectiveness. The architecture of a DCN directly impacts on its scalability, while its cost is largely driven by its power consumption. In this paper, we conduct a detailed survey of the most recent advances and research activities in DCNs, with a special focus on the architectural evolution of DCNs and their energy efficiency. The paper provides a qualitative categorization of existing DCN architectures into switch-centric and server-centric topologies as well as their design technologies. Energy efficiency in data centers is discussed in details with survey of existing techniques in energy savings, green data centers and renewable energy approaches. Finally, we outline potential future research directions in DCNs

A Partially Buffered Crossbar packet switching architecture and its scheduling

The crossbar fabric is widely used as the interconnect of high-performance packet switches due to its low cost and scalability. There are two main variants of the crossbar fabric: unbuffered and internally buffered. On one hand, unbuffered crossbar fabric switches exhibit the advantage of using no internal buffers. However, they require a centralized and complex scheduler. Internally buffered crossbar fabric switches, on the other hand, overcome the scheduling complexity by means of distributed schedulers. However, they require expensive internal buffers —one per crosspoint. In this paper we propose a novel architecture, namely the Partially Buffered Crossbar (PBC) switching architecture, where a small number of separate internal buffers are maintained per output. Our goal is to design a PBC switch having the performance of buffered crossbars and a cost comparable to that of unbuffered crossbars. We propose a class of round-robin scheduling algorithms for the PBC switch. Simulations results show that using as few as 8 buffers per output port and irrespective of the number, N, of input ports of the switch, we can achieve even better performance than buffered crossbars that use N buffers per output port.

Stellingen behorende bij het proefschrift Scheduling in High Performance Buffered Crossbar Switches van

1. The creation of the Internet is one step further for humankind to reach the speed of light. 2. The choice between circuit-switching and packet-switching boils down to which is “bandwidth-wise ” economically worth it: using more or wasting more. 3. The advantage of packet-switching, over circuit-switching, is statistical multiplexing. It is also the source of all its challenges. 4. Optimal switching performance cannot be obtained through distributed scheduling algorithms only; some sort of centralized knowledge is required. 5. The answer to: “I want a packet-switch that is scalable, has low latency and achieves high throughput ” is: “Choose two”. 6. If someone is considering to have telesurgery over the Internet, he is strongly advised to look elsewhere. 7. It is not because things are difficult that we do not dare, it is because we do not dare that they are difficult. 8. Knowledge is one of few resources on earth that multiplies when shared

High-performance scheduling algorithms for buffered crossbar switches

As we entered the new millennium, we swiftly moved from an industrial economy into an information economy, with the Internet playing a key part in revolutionizing our society and continuing, as it has done over the last decade, to experience explosive growth. With the rapid evolution and increasing capacity of high-bandwidth transmission links growing at the same speed as the Internet, packet switching and routing have become the bottleneck of today’s high-speed networks. Until recently, Internet routers and ATM switches were traditionally built around a central pool of shared memory buffers and a fast shared-bus backplane. However two main challenges have evolved out of the limitations in memory bandwidth and also interconnect technology: queue management and packet forwarding. Input queued crossbar-based switches (IQ) have largely been considered as a solution since they improve distribution of memory over each switch input and for their effective simultaneous transfer of packets due to the switched backplane. Input queued switches have gained heightened interest and demand, since they have low hardware requirements. The difficulty lies in the ability to design fast and simple schedulers to support the growing diversity of services, the Internet is expected to provide, continually making it harder for IQ switches to keep pace with the tremendous growth of the Internet. To meet these new demands, careful designs of the switching fabric, buffer architecture, and switching algorithms centered around IQ switches cannot be undertaken in order to reach aggregate data rates of multiple terabits per second and forwarding rates of billions of packets per second. In this thesis, we explore the basic architecture of routers and different types of switch fabrics. This includes IQ switches, combined input and output queued switches (CIOQ) and output queued switches (OQ) architectures. IQ switches and CIOQ switches architectures are based on the Virtual Output Queuing (VOQ) architecture. The two basic performance metrics for switches are throughput and delay respectively. They depend on both architecture choice and the scheduling policy. The well-known VOQ architecture affords the best example of high bandwidth switch capacity, compared to the FIFO architecture. It is the main purpose of this thesis, to address the two important issues of throughput and delay. We investigate an efficient switching architecture, along with a variety of scheduling algorithms, to achieve the above-mentioned goals in a Gigabit/Terabit networking environment. The investigated architecture, based on a one-cell internally buffered crossbar switch, along with the input VOQ architecture, improves the throughput of the switch and reduces the delay simultaneously. We illustrate its substantial advantages by making comparisons to the IQ crossbar based switches. We then propose a wide class of distributed scheduling algorithms and closely study their performance and stability properties. We then propose a class of practical scheduling algorithms that can be implemented in real-time for high input traffic. We also show how their distributed nature makes them desirable and in high demand for such ultra-capacity networks

Integrating Uni- and Multicast Scheduling in Buffered Crossbar Switches

Abstract — Internet traffic is a mixture of unicast and multicast flows. Integrated schedulers capable of dealing with both traffic types have been designed mainly for Input Queued (IQ) buffer-less crossbar switches. Combined Input and Crossbar Queued (CICQ) switches, on the other hand, are known to have better performance than their buffer-less predecessors due to their potential in simplifying the scheduling and improving the switching performance. The design of integrated schedulers in CICQ switches has thus far been neglected. In this paper, we propose a novel CICQ architecture that supports both unicast and multicast traffic along with its appropriate scheduling. In particular, we propose an integrated round robin based scheduler that efficiently services both unicast and multicast traffic simultaneously. Our scheme, named Multicast and Unicast Round robin Scheduling (MURS), has been shown to outperform all existing schemes while keeping simple hardware requirements. Simulation results suggested that we can trade the size of the internal buffers for the number of input multicast queues

Distributed Parallel Scheduling Algorithms for High-Speed Virtual Output Queuing Switches

Abstract—This paper presents a novel scalable switching architecture for input queued switches with its proper arbitration algorithms. In contrast to traditional switching architectures where the scheduler is implemented by one single centralized scheduling device, the proposed architecture connects several single scheduling devices in series and a distributed scheduling algorithm is run sequentially on them, whereby the inputs of each single scheduling device build connections to a group of outputs, considering both their local transmission requests as well as global outputs availability information. We show that a pipeline pattern can be used to increase the efficiency of the scheduling scheme with scheduling algorithms running in parallel on all the separate scheduling devices. We first introduce a distributed parallel round robin scheduling algorithm (DPRR) for the proposed architecture. Through the analysis of simulation results on various admissible traffics, it is shown that the performance of DPRR is much better than, or very close to the performance of, other round robin scheduling algorithms. We also prove that under Bernoulli i.i.d. uniform traffic DPRR achieves 100 % throughput. Secondly, we introduce a distributed parallel round robin scheduling algorithm with memory (DPRRM) as an improved version of DPRR to make it stable under any admissible traffic. I

Multicast Traffic Scheduling Based On High-Speed Crossbar Switches

Abstract — The tremendous growth of the Internet coupled with newly emerging applications has created a vital need for multicast traffic support by backbone routers and ATM switches. In this paper, we first introduce the multicast traffic scheduling problem. We focus our study on the multicast traffic scheduling in crossbar based input queued (IQ) switches. Due to the centralized scheduling complexity in IQ switches, growing interest is given to the buffered crossbar-based switching architecture, where a limited small amount of memory is embedded in each crosspoint of the crossbar fabric. In this paper, we show that a buffered crossbar switch can efficiently support multicast traffic and high throughput can be achieved with distributed and simple scheduling algorithms. Furthermore, we show that the presence of internal buffers is of key importance in optimizing the scheduling and the cost of the switch. Simulation results showed that the buffered crossbar based distributed scheduling algorithms achieve high performance under a wide range of realistic traffic patterns