Tras la pista de lo libertario

Es un hecho bastante común que al momento de abordar la cuestión libertaria, ya sea al nivel de la teoría como en el del sentido común, se la piense como un fenómeno capaz de sobrepasar todo tipo de coto u obstáculo que implique algún recorte en su expresión (sea del orden de lo material, político, cultural, moral o de cualquier otra especie): una especie de absoluto que por su fuerza irrefrenable se colocaría más cerca de lo utópico, más específicamente, como una ensoñación. Esa es una postura susceptible de adoptar diferentes valoraciones axiológicas, siendo el asumirla como uno de los mayores males que encuentran los hombres que quieren vivir en sociedad (de libertino o el de libertinaje) uno de las más recurrentes: lo libertario acaba con los pactos, los acuerdos, las leyes, y demás instituciones que rigen a las sociedades modernas. Obviamente, es una acepción que no contempla lo libertario como posibilidad efectiva de destrucción pero de ordenamientos que generan y reproducen desigualdades, dominaciones, marginalidad y exclusión. Y es tal perspectiva la que aquí nos interesa desarrollar. (Párrafo extraído del texto a modo de resumen)Mesa 3: El esquivo objeto de la ideologíaFacultad de Humanidades y Ciencias de la Educació

Parallelization of cycle-based logic simulation

Verification of digital circuits by Cycle-based simulation can be performed in parallel. The parallel implementation requires two phases: the compilation phase, that sets up the data needed for the execution of the simulation, and the simulation phase, that consists in executing the parallel simulation of the considered circuit for a certain number of cycles. During the early phase of design, compilation phase has to be repeated each time a bug is found. Thus, if the time of the compilation phase is too high, the advantages stemming from the parallel approach may be lost. In this work we propose an effective version of the compilation phase and compute the corresponding execution time. We also analyze the percentage of execution time required by the different steps of the compilation phase for a set of literature benchmarks. Further, we implemented the simulation phase exploiting the GPU architecture, and we computed the execution times for a set of benchmarks obtaining values comparable with literature ones. Finally, we implemented the sequential version of the Cycle-based simulation in such a way that the execution time is optimized. We used the sequential values to compute the speedup of the parallel version for the considered set of benchmarks

Simulator Semantics for System Level Formal Verification

Many simulation based Bounded Model Checking approaches to System Level Formal Verification (SLFV) have been devised. Typically such approaches exploit the capability of simulators to save computation time by saving and restoring the state of the system under simulation. However, even though such approaches aim to (bounded) formal verification, as a matter of fact, the simulator behaviour is not formally modelled and the proof of correctness of the proposed approaches basically relies on the intuitive notion of simulator behaviour. This gap makes it hard to check if the optimisations introduced to speed up the simulation do not actually omit checking relevant behaviours of the system under verification. The aim of this paper is to fill the above gap by presenting a formal semantics for simulators.Comment: In Proceedings GandALF 2015, arXiv:1509.0685

Anytime system level verification via parallel random exhaustive hardware in the loop simulation

System level verification of cyber-physical systems has the goal of verifying that the whole (i.e., software + hardware) system meets the given specifications. Model checkers for hybrid systems cannot handle system level verification of actual systems. Thus, Hardware In the Loop Simulation (HILS) is currently the main workhorse for system level verification. By using model checking driven exhaustive HILS, System Level Formal Verification (SLFV) can be effectively carried out for actual systems. We present a parallel random exhaustive HILS based model checker for hybrid systems that, by simulating all operational scenarios exactly once in a uniform random order, is able to provide, at any time during the verification process, an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability). We show effectiveness of the proposed approach by presenting experimental results on SLFV of the Inverted Pendulum on a Cart and the Fuel Control System examples in the Simulink distribution. To the best of our knowledge, no previously published model checker can exhaustively verify hybrid systems of such a size and provide at any time an upper bound to the Omission Probability

Mauricio Beuchot, La semiótica. Teorías del signo y el lenguaje en la historia, México, Fondo de Cultura Económica, 2004, 208 pp.

Fil: Massini Correas, Carlos I.

On minimising the maximum expected verification time

Cyber Physical Systems (CPSs) consist of hardware and software components. To verify that the whole (i.e., software + hardware) system meets the given specifications, exhaustive simulation-based approaches (Hardware In the Loop Simulation, HILS) can be effectively used by first generating all relevant simulation scenarios (i.e., sequences of disturbances) and then actually simulating all of them (verification phase). When considering the whole verification activity, we see that the above mentioned verification phase is repeated until no error is found. Accordingly, in order to minimise the time taken by the whole verification activity, in each verification phase we should, ideally, start by simulating scenarios witnessing errors (counterexamples). Of course, to know beforehand the set of such scenarios is not feasible. In this paper we show how to select scenarios so as to minimise the Worst Case Expected Verification Tim

Nota sobre el Rule of Law y la ética de la virtud

Fil: Massini Correas, Carlos I.

Gordon Thomas, Los judíos del Papa. El plan secreto del Vaticano para salvar a los judíos de los nazis, trad. T. Arijón, Buenos Aires, Edhasa, 2013, 354 pp.

Fil: Massini Correas, Carlos I.. Universidad de Mendoz

Jean Grondin ¿Qué es la Hermenéutica? Trad. A. Martínez Riu, Barcelona, Herder, 2008, 174 pp.

Fil: Massini Correas, Carlos I.. Universidad de Mendoz