Modified Distributive Arithmetic based 2D-DWT for Hybrid (Neural Network-DWT) Image Compression

Artificial Neural Networks ANN is significantly used in signal and image processing techniques for pattern recognition and template matching Discrete Wavelet Transform DWT is combined with neural network to achieve higher compression if 2D data such as image Image compression using neural network and DWT have shown superior results over classical techniques with 70 higher compression and 20 improvement in Mean Square Error MSE Hardware complexity and power issipation are the major challenges that have been addressed in this work for VLSI implementation In this work modified distributive arithmetic DWT and multiplexer based DWT architecture are designed to reduce the computation complexity of hybrid architecture for image compression A 2D DWT architecture is designed with 1D DWT architecture and is implemented on FPGA that operates at 268 MHz consuming power less than 1

Awareness and Use pattern of Electronic Resources among the Doctoral Research Scholars of Central University of Tamil Nadu, Tiruvarur, India: A study

This paper\u27s main objective is to examine the awareness and use pattern of electronic resources by doctoral research scholar’s community of the Central University of Tamil Nadu. The investigator adopted a survey method used for the study. Structured questionnaires were administered to the 100 respondents to collect data for the study and returned questionnaires were analysed using simple percentage by the SPSS software. Findings of the survey revealed that the majority of doctoral students aware of electronic resources and user education/training programs are the most important for maximum utilization of electronic resources in University Library

Basic Understanding of Developing Writing Skills in Teaching and Learning in ESL Classroom

Language skills are crucial for effective communication and human development, serving as easily distinguishable signs that guide human development. One of the things that set humans apart from other animals is language, and writing is vital to humans in many ways because it facilitates learning. English is the language that connects people globally. One of the major challenges that ESL teachers face today is developing students' writing abilities.  Writing is regarded as the most challenging and significant of the four language skills. Writing is a skill that can only be developed through extensive exposure to speaking, listening, and reading. Developing competence in writing skills is an essential part of achieving success in academic records. Unconsciously learned material is reflected in one powerful writing assignment. Writing is measured as a domineering proficiency for prosperous language development. Thus, this study aims to look into the practical difficulties that both students and teachers face when learning and teaching writing skills for academic purposes, as well as to suggest ways to improve writing skills. ESL learners need to develop writing skills, and this paper discusses various methods for doing so

A CLOSED-FORM ENERGY REAP SCHEME WITH FINEST ALTERATION COMPETENCE

A shut-form power expression and custom control formula for regulating a switched-capacitor Electricity-Electricity ripper tools with optimal conversion efficiency are suggested within this paper. The look and simulation of the fully integrated circuit in line with the suggested power managing approach is presented. Within an energy harvesting sensor, an electrical management circuit is needed to manage the variable harvested current to supply a constant supply rail for that sensor circuits. Energy harvesting is definitely an emerging technology for powering wireless sensor nodes, enabling battery-free operation of those devices. The ability management circuit must be compact, efficient, and powerful towards the variations from the input current and cargo current. The suggested regulation formula instantly adjusts both current gain and switching frequency of the switched-capacitor Electricity-Electricity ripper tools according to its input current and cargo current, growing the ability efficiency across a large input current range. This power management circuit continues to be simulated inside a .25 standard CMOS process and simulation results make sure by having an input current varying from .5 V to two.5 V, the ripper tools can produce a controlled 1.2 V output rail and generate a maximum load current of 100

IOT BASED HOME AUTOMATION

The purpose of this project is to monitoring and controlling electrical devices in home remotely using Wi-Fi and get the status alert through SMS by using GSM modem whenever Required. The GSM modem provides the communication mechanism between the user and the microcontroller system by means of SMS. User can monitor the status and also control multiple electrical devices by sending suitably formatted SMS to the microcontroller based control system. These SMS commands are interpreted by microcontroller system and are validated. If the SMS command received is valid that means if password is matched then it takes the necessary action on the said devices and also it always monitors the home, if any one crosses the fencing then alerts will be sent to owners mobile in the form of SMS

DESIGN OF 4-BIT MCC ADDERS TO IMPROVE PROCESSOR SPEED IN VLSI

Enhance the processer speed by diminishing the convey delay furthermore decreased the power utilization. The testing paradigm of profound submicron advancements is low-power and fast correspondence computerized flag preparing chips. The execution of numerous applications as advanced flag handling relies on the execution of the math circuits to execute complex Algorithms. Quick number juggling calculation cells including adders are the most often and generally utilized circuits as a part of extensive scale combination (VLSI) frameworks. More over decrease of the power utilization is the basic worry in this field. Presently now a days there is at colossal interest for compact electronic gadgets, the architects are headed to take a stab at littler silicon region, higher speed, and longer battery life. Viper is the center component of complex number-crunching circuits like expansion, duplication, division, exponentiation, et cetera. Static CMOS circuits comprised of a corresponding PMOS as draw up and NMOS as draw down networks. Majority of the circuit outlines are as yet utilizing this as it gives low commotion, low power and quick speed. The principle preferred standpoint of CMOS over NMOS and bipolar is much littler power dissemination. Rationed circuit supplanted the pull up PMOS arrange by associating it to a ground. By interfacing PMOS to a ground, there is an extraordinary diminishment in the draw up transistors utilized when utilized as a part of an unpredictable plan. Dynamic circuit is like ratioed circuit however the PMOS is attached to a clock. PMOS is not generally on as it is controlled by the deliberately arranged clock. Range, deferral and power are the three for the most part acknowledged outline measurements to quantify the nature of a circuit or to think about different styles of circuits. The most generally utilized rationale [1] style is static correlative CMOS. The static CMOS style is truly an expansion of the static CMOS inverter to various data sources. In audit, the essential favorable position of the CMOS structure is vigor (i.e., low affectability to clamor), great execution, and low power utilization (with no static power utilization). As we will see, the greater part of those properties are persisted to substantial fan-in rationale entryways actualized utilizing a similar circuit topology. In this work, we endeavor to address these weaknesses of utilizing DFTL as a part of rationale operations with an examination on the ideal measuring proportion and a "timing window" strategy. For correlation purposes, the vitality versus delay (E-D) conduct of indistinguishable 64-bit Sklansky convey combine tree executed in DFTL, CDL, dynamic rationale, and static rationale doors is broke down

THE METHODS OF IMPROVING THE SPEED OF CLA ADDERS IN DOMINO LOGIC

Adders are the critical parts of processor circuits. The performance of processors increases by improving the performance and functionality of adders. Carry look-ahead (CLA) adder’s principle remains dominant in High-speed adder architectures, so the carry delay can be improved by calculating each stage in parallel. In this paper by using an 4-bit Manchester carry chain (MCC) adder block in multi output domino CMOS logic. The even and odd carries of this adder are computed in parallel by two independent 2-bit carry chains. Implementation of wider adders based on the use of 4-bit adder module improves the operating speed compared to adders based on the standard 4-bit MCC adder module. Proposed design technique can be used for the implementation of 4, 8, 16 and 32 bit adders in multi output domino logic by using mentor graphics

LOW POWER TEST DATA COMPRESSION AND POWER MINIMIZATION METHODS FOR DIGITAL VLSI CIRCUITS

The measure of data required to test ICs are expanding quickly with the improvements of innovation. Likewise, outline of low-power superior compact registering gadgets has turned into a noteworthy target for the outline engineers. Notwithstanding, diminishment of power scattering is a basic parameter for configuration engineers, as well as for DFT builds as the framework devour considerably more power amid test than amid ordinary operation. In this way, low-power test data pressure for digital VLSI frameworks has turned into a noteworthy sympathy toward specialists and researchers of these ranges as of late. Because of the expansion in the test data volume and high test power, this range has dependably been effectively looked into on and various test data pressure and power decrease methods are presented. This part audits the significant test data pressure and power minimization systems proposed in the writing