Monte Carlo simulation of implant free InGaAs MOSFET

The performance potential of n-type implant free In0.25Ga0.75As MOSFETs with high-κ dielectric is investigated using ensemble Monte Carlo device simulations. The implant free MOSFET concept takes advantage of the high mobility in III-V materials to allow operation at very high speed and low power. A 100 nm gate length implant free In0.25Ga0.75As MOSFET with a layer structure derived from heterojunction transistors may deliver a drive current of 1800 A/m and transconductance up to 1342 mS/mm. This implant free transistor is then scaled in the both lateral and vertical dimensions to gate lengths of 70 and 50 nm. The scaled devices exhibit continuous improvement in the drive current up to 2600 A/m and 3259 A/m and transconductance of 2076 mS/mm and 3192 mS/mm, respectively. This demonstrates the excellent scaling potential of the implant free MOSFET concept

Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga<sub>2</sub>O<sub>3</sub> or a stack of Ga<sub>2</sub>O<sub>3</sub> and Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub>. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si delta-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> is included in a stack with 1 nm of Ga<sub>2</sub>O<sub>3</sub> at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ~3 V. However, the inclusion of Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in the gate insulator introduces many oxide states (≤4.70Ã�Â�10<sup>12</sup> cm<sup>âÂ�Â�2</sup>). Transmission electron microscope images of the interface region show that the growth of a Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer on Ga<sub>2</sub>O<sub>3</sub> disturbs the well ordered Ga<sub>2</sub>O<sub>3</sub>/GaAs interface. We therefore conclude that while including Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in a dielectric stack with Ga<sub>2</sub>O<sub>3</sub> is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga<sub>2</sub>O<sub>3</sub>/GaAs interface and near interface region by introducing roughness and a large number of defect states

180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

Abstract: Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions

Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

No abstract available

Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs

The performance of 300nm, 500nm and 1μm metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-κ (κ=20) dielectric stack grown upon a δ-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 μm to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 μA/μm and extrinsic transconductance of 400 µS/µm are obtained from these devices. Gate leakage current of less than 100pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance submicron enhancement mode III-V MOSFETs reported to date

Nanoparticle Tracking Analysis for the Enumeration and Characterization of Mineralo-Organic Nanoparticles in Feline Urine

Urinary stone disease, particularly calcium oxalate, is common in both humans and cats. Calcifying nanoparticles (CNP) are spherical nanocrystallite material, and are composed of proteins (fetuin, albumin) and inorganic minerals. CNP are suggested to play a role in a wide array of pathologic mineralization syndromes including urolithiasis. We documented the development of a clinically relevant protocol to assess urinary CNP in 9 healthy cats consuming the same diet in a controlled environment using Nanoparticle Tracking Analysis (NTA®). NTA® is a novel method that allows for characterization of the CNP in an efficient, accurate method that can differentiate these particles from other urinary submicron particulates. The predominant nanoscale particles in feline urine are characteristic of CNP in terms of their size, their ability to spontaneously form under suitable conditions, and the presence of an outer layer that is rich in calcium and capable of binding to hydroxyapatite binders such as alendronate and osteopontin. The expansion of this particle population can be suppressed by the addition of citrate to urine samples. Further, compounds targeting exosomal surfaces do not label these particulates. As CNP have been associated with a number of significant urologic maladies, the method described herein may prove to be a useful adjunct in evaluating lithogenesis risk in mammals

Enhancement Mode n-MOSFET with High-κ Dielectric on GaAs Substrate

In this paper, we report MOS heterostructures grown by molecular beam epitaxy on III-V substrates, employing a high-κ dielectric stack comprised of gallium oxide and gadolinium gallium oxide. Mobilities exceeding 12,000 and 6,000 cm2/Vs, for sheet carrier concentration ns of about 2.5x1012 cm-2 were measured on MOSFET structures on InP and GaAs substrates, respectively. These structures were designed for enhancement mode operation and include a 10 nm thick strained InGa1-xAs channel layer with In mole fraction x of 0.3 and 0.75 on GaAs and InP substrates, respectively

Carrier-envelope phase effects on the strong-field photoemission of electrons from metallic nanostructures

Sharp metallic nanotapers irradiated with few-cycle laser pulses are emerging as a source of highly confined coherent electron wavepackets with attosecond duration and strong directivity. The possibility to steer, control or switch such electron wavepackets by light is expected to pave the way towards direct visualization of nanoplasmonic field dynamics and real-time probing of electron motion in solid state nanostructures. Such pulses can be generated by strong-field induced tunneling and acceleration of electrons in the near-field of sharp gold tapers within one half-cycle of the driving laser field. Here, we show the effect of the carrier-envelope phase of the laser field on the generation and motion of strong-field emitted electrons from such tips. This is a step forward towards controlling the coherent electron motion in and around metallic nanostructures on ultrashort length and time scales

1 μm gate length, In_0.75Ga_0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737μS/μm

The first demonstration of implant-free, flatband-mode In<sub>0.75</sub>Ga<sub>0.25</sub>As channel n-MOSFETs is reported. These 1 μm gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm<sup>2</sup>/Vs and sheet carrier concentration of 3.3×10<sup>12</sup> cm<sup>-22</sup>, utilise a Pt gate, a high-k dielectric (k≈20), and a δ-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (I<sub>d,sat</sub>) of 933 μA/μm, extrinsic transconductance (g<sub>m</sub>) of 737 μS/μm, gate leakage (I<sub>g</sub>) of 40 pA, and on-resistance (R<sub>on</sub>) of 555 Ωμm. The g<sub>m</sub> and R<sub>on</sub> figures of merit are the best reported to date for any III-V MOSFET

High Mobility III-V MOSFETs For RF and Digital Applications

Developments over the last 15 years in the areas of materials and devices have finally delivered competitive III-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/Ga2O3 MOS systems, presents GaAs MOSFET DC and RF data, and concludes with an outlook for high indium content channel MOSFETs. GaAs based MOSFETs are potentially suitable for RF power amplification, switching, and front-end integration in mobile and wireless applications while MOSFETs with high indium content channels are of interest for future CMOS applications