Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Abstract

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga<sub>2</sub>O<sub>3</sub> or a stack of Ga<sub>2</sub>O<sub>3</sub> and Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub>. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si delta-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> is included in a stack with 1 nm of Ga<sub>2</sub>O<sub>3</sub> at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ~3 V. However, the inclusion of Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in the gate insulator introduces many oxide states (≤4.70Ã�Â�10<sup>12</sup> cm<sup>âÂ�Â�2</sup>). Transmission electron microscope images of the interface region show that the growth of a Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer on Ga<sub>2</sub>O<sub>3</sub> disturbs the well ordered Ga<sub>2</sub>O<sub>3</sub>/GaAs interface. We therefore conclude that while including Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in a dielectric stack with Ga<sub>2</sub>O<sub>3</sub> is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga<sub>2</sub>O<sub>3</sub>/GaAs interface and near interface region by introducing roughness and a large number of defect states