Minimization of Parity-Checked Fault-Secure AND/EXOR Networks

We present a new algorithm for the efficient realization of fault-secure and totally self-checking circuits for multi-output boolean functions using parity-checked AND/EXOR networks. First results on the minimization of a large set of typical arithmetic and random functions and several MCNC benchmark circuits show that AND/EXOR networks often allow much better solutions than traditional AND/OR networks. The overhead for the realization of the parity output may be as low as a few percent. 1 Introduction The realization of boolean switching functions using AND/EXOR networks is very attractive from a theoretical point of view. In fact, it has been conjectured that the AND/EXOR networks on the average require fewer product terms than AND/OR PLA's [10]. Another well known advantage of the AND/EXOR logic is the excellent testability. However, up to now they were used in special application areas only, due to the lack of circuit technology and easily available synthesis tools. Recent progre..