REXIB: Remote Experiments Interface Builder

Remote Experimentation is an educational resource that allows teachers to strengthen the practical contents of science & engineering courses. However, building up the interfaces to remote experiments is not a trivial task. Although teachers normally master the practical contents addressed by a particular remote experiment they usually lack the programming skills required to quickly build up the corresponding web interface. This paper describes the automatic generation of experiment interfaces through a web-accessible Java application. The application displays a list of existent modules and once the requested modules have been selected, it generates the code that enables the browser to display the experiment interface. The tools main advantage is enabling non-tech teachers to create their own remote experiments

Remote experimentation network - yielding an inter-university peer-to-peer e-service

The goal of this paper is to discuss the benefits and challenges of yielding an inter-continental network of remote laboratories supported and used by both European and Latin American Institutions of Higher Education. Since remote experimentation, understood as the ability to carry out real-world experiments through a simple web browser, is already a proven solution for the educational community as a supplement to on-site practical lab work (and in some cases, namely for distance learning courses, a replacement to that work), the purpose is not to discuss its technical, pedagogical, or economical strengths, but rather to raise and try to answer some questions about the underlying benefits and challenges of establishing a peer-to-peer network of remote labs. Ultimately, we regard such a network as a constructive mechanism to help students gain the working and social skills often valued by multinational/global companies, while also providing awareness of local cultural aspects

Biomimetic polysaccharide/bioactive glass nanoparticles multilayer membranes for guided tissue regeneration

Nowadays, guided tissue regeneration (GTR) research is centred in the development of composite bioabsorbable membranes with enhanced bioactivity and with processing controlled at the nanoscale. Inspired by this new focus of GTR research and also by nacre structure, layered freestanding membranes were produced using the Layer-by-Layer (LbL) deposition technique, combining chitosan (CHI), hyaluronic acid (HA) and bioactive glass nanoparticles (BGNPs). It is expected that the combination of these materials processed by this particular technique will result in nanostructured membranes with enhanced mechanical performance as well as improved bioactivity. Moreover, the effect of the modification of HA with catechol groups (HAD) on the adhesive properties of the membranes was also analysed. The results showed that it was possible to produce biomimetic membranes with different surface properties, improved adhesive strength and the ability to induce the formation of apatite, necessary for the formation of new bone. It was also possible to control the BGNPs content of the membranes by use of HAD instead of unmodified HA and changing the number of BGNPs' deposition steps. Moreover, it was shown that membranes with different concentrations of BGNPs possess different mechanical performance, swelling properties and degradation behaviour, which indicates the possibility to tune the membranes' properties by controlling the deposition of BGNPs onto the membranes

Neutrino magnetohydrodynamics

A new neutrino magnetohydrodynamics (NMHD) model is formulated, where the effects of the charged weak current on the electron-ion magnetohydrodynamic fluid are taken into account. The model incorporates in a systematic way the role of the Fermi neutrino weak force in magnetized plasmas. A fast neutrino-driven short wavelengths instability associated with the magnetosonic wave is derived. Such an instability should play a central role in strongly magnetized plasma as occurs in supernovae, where dense neutrino beams also exist. In addition, in the case of nonlinear or high frequency waves, the neutrino coupling is shown to be responsible for breaking the frozen-in magnetic field lines condition even in infinite conductivity plasmas. Simplified and ideal NMHD assumptions were adopted and analyzed in detail

A novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs

This poster presents the first truly non-intrusive structural concurrent test approach, with the objective of testing partially and dynamically reconfigurable SRAM-based FPGAs without disturbing their operation. This is accomplished by using a new methodology to carry out the replication of active Configurable Logic Blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system

Run-time management of logic resources on reconfigurable systems

Dynamically reconfigurable systems based on partialand dynamically reconfigurable FPGAs may have theirfunctionality partially modified at run-time withoutstopping the operation of the whole system.The efficient management of the logic space availableis one of the biggest problems faced by these systems.When the sequence of reconfigurations to be performed isnot predictable, resource allocation decisions have to bemade on-line. A rearrangement may be necessary to getenough contiguous space to implement incomingfunctions, avoiding the spreading of their components andthe resulting degradation of system performance.A new software tool that helps to handle the problemsposed by the consecutive reconfiguration of the same logicspace is presented in this paper. This tool uses a novel on--line rearrangement procedure to solve fragmentationproblems and to rearrange the logic space in a waycompletely transparent to the applications currentlyrunnin

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead

Programmable logic devices: a test approach for the Input / Output blocks and Pad-to-Pin interconnections

Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation of the whole system. The efficient management of the logic space available is one of the biggest problems faced by these systems. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. A rearrangement may be necessary to get enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance.A new software tool that helps to handle the problems posed by the consecutive reconfiguration of the same logic space is presented in this paper. This tool uses a novel on-line rearrangement procedure to solve fragmentation problems and to rearrange the logic space in a way completely transparent to the applications currently running

A Framework for implementing radiation-tolerant circuits on reconfigurable FPGAs

The outstanding versatility of SRAM-based FPGAs make them the preferred choice for implementing complex customizable circuits. To increase the amount of logic available, manufacturers are using nanometric technologies to boost logic density and reduce prices. However, the use of nanometric scales also makes FPGAs particularly vulnerable to radiation-induced faults, especially because of the increasing amount of configuration memory cells that are necessary to define their functionality. This paper describes a framework for implementing circuits immune to radiation-induced faults, based on a customized Triple Modular Redundancy (TMR) infrastructure and on a detection-and-fix controller. This controller is responsible for the detection of data incoherencies, location of the faulty module and restoration of the original configuration, without affecting the normal operation of the mission logic. A short survey of the most recent data published concerning the impact of radiation-induced faults in FPGAs is presented to support the assumptions underlying our proposed framework. A detailed explanation of the controller functionality is also provided, followed by an experimental case study

IEEE 1149.1 compliance-enable pin(s): a solution for embedded microprocessor-based systems debug and test

Microprocessor-based systems are usually debugged with the help of in-circuit emulators and logic analysers. However, these traditional debug tools cannot be used when the microprocessor is an embedded core. To overcome this problem we propose the use of an embedded debug and test infrastructure and the IEEE 1149.1 compliance-enable mode to implement the basic functionality provided by an In-circuit emulator and a logic analyser.N/