Soft sphere model for electron correlation and scattering in the atomistic modelling of semiconductor devices

The atomistic modelling of silicon MOSFET devices becomes essential at deep sub-micron scales when it is no longer possible to represent the charged impurities by a continuous charge distribution with a determined doping density. Instead the spatial distribution and the actual number of dopants must be treated as discrete random variables. The present paper addresses the issue of modelling the dynamics of discrete carrier flow in a semiconductor device utilising a simple model of the carrier-carrier scattering and carrier-fixed impurity scattering which is suitable for efficient simulations of large ensembles of devices

Efficient hole transport model in warped bands for use in the simulation of Si/SiGe MOSFETs

An analytical geometric model for the valence band in strained and relaxed Si1-xGex is presented, which shows good agreement with a 6-band k·p analysis of the valence band. The geometric model allows us to define an effective mass tensor for the warped valence band structure. The model also has applications in the study of III-V semiconductors, and could aid in the interpretation of cyclotron resonance experiments in these bands. A warped three-band Monte Carlo simulation has been developed based on this model making use of the efficient calculation of trajectory dynamics that is made possible through the use of such a model. The calculated transport characteristics show good agreement with the available experimental data

A study of the impact of dislocations on the thermoelectric properties of quantum wells in the Si/SiGe materials system

Thermoelectric materials generate electricity from thermal energy using the Seebeck effect to generate a voltage and an electronic current from a temperature difference across the semiconductor. High thermoelectric efficiency ZT requires a semiconductor with high electronic conductivity and low thermal conductivity. Here, we investigate the effect of scattering from threading dislocations of edge character on the thermoelectric performance of individual n and p-channel SiGe multiple quantum well structures. Our detailed physical simulations indicate that while the thermal and electrical conductivities decrease with increasing dislocation scattering/density, the Seebeck coefficient actually increases with increasing threading dislocation density above 10<sup>6</sup> cm<sup>-2</sup> at room temperature, due to an increase in the entropy associated with each carrier. The collective result of these individual effects, is that the present Si-based quantum well designs can tolerate scattering by a threading dislocation density up to ~10<sup>8</sup> cm<sup>-2</sup>, well within the capabilities of modern growth techniques, before significant reductions in ZT due to scattering from threading dislocations is observed

Nonequilibrium hole transport in deep sub-micron well-tempered Si p-MOSFETs

Using 2D full-band MC simulations the authors study nonequilibrium transport effects and the performance potential of well tempered Si p-channel MOSFETs covering gate lengths ranging from 90nm to 25nm. By comparing MC simulations with carefully calibrated drift diffusion (DD) simulations of the same devices, they provide a quantitative estimate of the importance and the influence of nonequilibrium transport on the device performance

Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail

Scaling study of Si/SiGe MODFETs for RF applications

Based on the successful calibration on a 0.25 /spl mu/m strained Si/SiGe n-type MODFET, this paper presents a gate length scaling study of double-side doped Si/SiGe MODFETs. Our simulations show that gate length scaling improves device RF performance. However, the short channel effects (SCE) along with the parasitic delays limit the device performance improvements. We find that it is necessary to consider scaling (dimensions and doping) of both the lateral and vertical architecture in order to optimize the device design

Simulation of direct source-to-drain tunnelling using the density gradient formalism: Non-Equilibrium Greens Function calibration

Quantum mechanical confinement effects, gate, hand-to-hand and source-to-drain tunnelling will dramatically affect the characteristics of future generation nanometre scaled devices. It has been demonstrated already that first-order quantum corrections, which satisfactorily describe quantum confinement effects, can be introduced into efficient TCAD orientated drift-diffusion simulators using the density gradient approach. In this paper we refer to Non-Equilibrium Green's Function simulations in order to calibrate the density gradient formalism in respect of both confinement and source-to-drain tunnelling using different effective masses in directions normal and parallel to the conducting channel. We demonstrate that the density gradient formalism can describe accurately the current characteristics in sub 20 nm double gate MOSFETs

Indication of Non-equilibrium Transport in SiGe p-MOSFETs

No abstract avaliable

Enhanced velocity overshoot and transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - predictions for deep submicron devices

No abstract avaliable

Improved effective mobility extraction in MOSFETs

The standard method of extracting carrier effective mobility from electrical measurements on MOSFETs is reviewed and the assumptions implicit in this method are discussed. A novel technique is suggested that corrects for the difference in drain bias during IV and CV measurements. It is further shown that the lateral field and diffusion corrections, which are both commonly neglected, in fact cancel. The effectiveness of the proposed technique is demonstrated by application to data measured on a quasi-planar SOI finFET at 300 K and 4 K