Asenov, A.

Barker, J.R.

Braithwaite, G.

Evans, A.G.R.

Kaya, S.

Palmer, M.J.

Parker, E.H.C.

Prest, M.J.

Waite, A.M.

Watling, J.R.

Whall, T.E.

Zhao, Y.P.

English

Palmer, MJ

Braithwaite, G

Prest, MJ

Parker, EHC

Whall, TE

Zhao, S

Kaya, S

Watling, JR

Asenov, A

Barker, JR

Waite, AM

Evans, AGR

Enlighten: Publications

Enhanced velocity overshoot and transconductance in Si/SiGe/Si pMOSFETs - predictions for deep submicron devices

 
 
 
 
 
 
Palmer, M.J. and Braithwaite, G. and Prest, M.J. and Parker, E.H.C. and 
Whall, T.E. and Zhao, Y.P. and Kaya, S. and Watling, J.R. and Asenov, 
A. and Barker, J.R. and Waite, A.M. and Evans, A.G.R. (2001) Enhanced 
Velocity Overshoot and Transconductance in Si/Si(0.64)Ge(0.36)/Si 
pMOSFETs - Predictions for Deep Submicron Devices. In, Ryssel, H. 
and Wachutka, G. and Grunbacher, H., Eds. Solid State Device Research 
Conference, 11-13 September 2001, pages pp. 199-202, Nuremburg, 
Germany.
 
 
 
 
 
 
http://eprints.gla.ac.uk/3013/ 
 
 
 
 
Glasgow ePrints Service 
http://eprints.gla.ac.uk 
Enhanced Velocity Overshoot and Transconductance in
Si/Si0.64Ge0.36/Si pMOSFETs - Predictions for Deep Submicron
Devices
M. J. Palmer, G. Braithwaite, M. J. Prest, E. H. C. Parker and T. E. Whall
Dept of Physics, University of Warwick, Coventry CV4 7AL, England
E-mail: Martin.Palmer@warwick.ac.uk
Y. P. Zhao, S. Kaya, J. R. Watling, A. Asenov and J. R. Barker
Device Modelling Group, University of Glasgow, G12 8LA, Scotland
A. M. Waite and A. G. R. Evans
Department of Electronics and Computer Science, University of
Southampton, Highfield, Southampton, SO17 1BJ, England
Abstract
Electrical measurements have been
carried out on Si/Si0.64Ge0.36/Si pMOS
devices and it is demonstrated that
enhanced low field carrier mobilities lead
to concomitant and substantial enhance-
ments in velocity overshoot and
transconductance at deep submicron
channel lengths. This provides considerable
motivation for incorporating SiGe into Si
MOS technology.
1. Introduction
There is much interest in fully pseudo-
morphic Si/SiGe/Si structures for Si-CMOS
applications with a major objective of
realising symmetrical CMOS with matching
p-channel/n-channel performance [1].
However, whereas performance enhance-
ments are impressive - factors of two or
more at large channel lengths (>3 µm) [2],
they are only modest for channel lengths of
about 0.5 µm [3,4]. CMOS channel lengths
are now, of course, approaching 0.1 µm but
there are only a few reports on SiGe
devices of this geometry. Whereas current
drive enhancements of about a factor of two
have been demonstrated at deep submicron
compared to silicon controls, [5,6] the
absolute values of current fall short of state-
of-the-art silicon. There is therefore an
urgent need for more work. The present
paper puts the disappointing results at 0.5
µm into perspective and provides strong
motivation for further investigations at
0.1 µm and below. Electrical measurements
have been carried out at 77K in order to
access higher (but realistic) mobilities,
which otherwise would have to be obtained
by the much more challenging route of
maintaining materials quality in a fully
processed pseudomorphic device.
Alternatively, high mobilities may be
achieved by the use of high-germanium
content layers grown pseudomorphically on
SiGe virtual substrates. However, the
production of virtual substrates of sufficient
quality for MOS technologies remains a
major challenge and the subject of much
study. At this stage their use can only be
anticipated. The current investigation
follows those of Kaya et al. [7] and Zhao et
al. [8], in which we reported enhanced
velocity overshoot as compared to silicon in
Si/Si0.8Ge0.2/Si structures [7] and in the
present devices [8] at 300K. It provides
further support for the analysis given there.
The previous works extend the analysis
to include energy transfer and Monte-Carlo
simulations. They show that the origin of
the velocity overshoot enhancement derives
essentially from increased energy relaxation
times in SiGe coupled with improved low
field mobilities.
2. Fabrication, Measurement
and Modelling
We have measured and modelled the
drain characteristics of nominal
Si/Si0.64Ge0.36/Si pMOS devices of different
effective channel lengths 0.35 < Leff < 10
µm and nominal silicon cap thicknesses
2 nm ≤ tcap ≤ 8 nm. The detailed specifica-
tions, fabrication and effective mobilities of
those devices at 300K have been previously
discussed [9].
A schematic of the MOSFET structure is
shown in figure 1 and the measured
characteristics of a 8 nm silicon cap device
are shown in figure 2. Using a commercial
2D device simulator [10] and empirical
expressions for the vertical and horizontal
field dependence of the carrier drift velocity
we have obtained good fits to the data, also
shown in figure 2.
3. Results and Discussion
From the model we have extracted the
apparent saturation drift velocities, satυ~ ,
given in figure 3. We note first of all that
the long channel value of satυ~ in SiGe is
less than that of silicon. In previous papers
we have argued [9,11,12] that the low field
room temperature mobility in these
heterostructures is limited by interface
roughness scattering. However, it has been
shown [13,14] that alloy scattering
increases by orders of magnitude in high
horizontal fields and this is a possible
explanation of the low value of satυ~ in the
alloy. The small value of satυ~ means that
the current drive/transconductance at 0.5µm
VDS (V)
-5-4-3-2-10
I D
S
(µ
A
/µ
m
)
-500
-400
-300
-200
-100
0
VGS=-5V
VGS=-4V
VGS=-3V
VGS=-2V
VGS=-1V
Figure 2. Example measured (+) and
simulated () current characteristics:
SiGe, 8 nm Si cap, Leff = 0.35 µm.
Si (substrate) n+ 2×1017 cm-3
Si (buffer) n+ 100 nm
Source
p+
Drain
p+
Si0.64Ge0.36 10 nm
SiO2 10 nm
p-poly Si gate
Si cap
L
Figure 1. Schematic of the MOSFET
structure
is not substantially enhanced compared to
silicon, in spite of the higher mobility [4].
However, as the channel length decreases,
we observe a dramatic increase in satυ~ in the
SiGe devices, substantially larger than in
the silicon controls, which is attributed to
velocity overshoot.
Following the analysis of Roldan et al.
[15], we fit the drift velocity data to:
2
||
~
LV
dxdE
DSasat
satsat
λυ
λυυ
+≈
+=
where satυ is the velocity in a homogeneous
field, dxdE|| is the gradient of the electric
field parallel to the surface and λ and
aλ are fitting parameters. Figure 4 shows
satυ~ versus 1/L
2 for the various devices.
Using the aλ values obtained from figure 4
we can predict the saturation transconduc-
tance enhancement from the form [15]
 
 
 
 








+
+
=
L
L
V
VC
L
W
g a
DS
sat
DSGCm
λ
υ
µ
µ
1
where CGC is the gate to channel capaci-
tance and µ is the low lateral field mobility
corresponding to the average vertical field
in the device with VGS=-1V (to restrict
transport to the SiGe channel) and VDS=-
3.3V. Table 1 shows a comparison of the
Leff (µm)
0.1 1
g m
,S
iG
e
/g
m
,S
i
0.5
1.0
1.5
2.0
2 nm cap
5 nm
cap
8 nm
cap
Figure 5. Predicted enhancement of
saturation transconductance for SiGe
samples compared to silicon control.
Leff (µm)
1 10
v s
at
(1
06
cm
/s
)
4
6
8
10
12
~
Figure 3. Fitted values of satv~ versus
gate length for SiGe samples with 2
nm (  ) 5 nm () and 8 nm () caps
and Si control ().
1/Leff
2 (µm-2)
0 2 4 6 8 10 12
v s
at
(1
06
cm
/s
)
4
6
8
10
12
2 nm
cap
Si con
trol
8 n
m c
ap
5 n
m c
ap
~
Figure 4. satv~ versus 1/Leff
2 for SiGe
samples and Si control. The 5 and 8
nm data points are omitted for clarity.
The trend is similar but with more
scatter.
Table 1. Peak low field mobility at
300K [9] and 77K.
Sample µ77K
(cm2/Vs)
µ300K
(cm2/Vs)
2 nm cap 569 162
5 nm cap 796 217
8 nm cap 1454 305
Si control 322 128
peak values of measured mobility at 77K
and at room temperature. The ratios
between the intrinsic transconductances of
the SiGe samples and the Si control, taking
account of the variation of CGC with vertical
architecture, are plotted against channel
length in figure 5. The model predicts up to
a factor of 1.9 improvement at Leff = 0.07
µm.
4 Conclusions
Si0.64Ge0.36 p-channel MOSFETs operating
at 77K have been investigated in an attempt
to probe a high-mobility region of
operation. An enhanced apparent saturation
velocity at short channel lengths indicates
velocity overshoot. The results are
extrapolated to deep submicron gate
lengths, predicting significant improve-
ments in the transconductances of devices
containing a SiGe channel. We expect
similar enhancements at room temperature,
especially as the low field mobilities can be
improved. Even with existing devices, a
rough estimate using the same extrapolation
with the room temperature analysis [8]
predicts a factor of 1.4 enhancement at Leff
= 0.07 µm. Notwithstanding the limitations
of the present simulation methods
[7,15,16], the enhancements predicted for
Leff ≤ 0.07 µm should provide considerable
encouragement for those seeking to
fabricate SiGe MOS devices at small
geometries.
5. References
[1] T. E. Whall and E. H. C. Parker, “SiGe heterostruc-
tures for FET applications” J. Phys. D. Vol 31, 1998, pp.
1397–1416.
[2] S. P. Voignegescu, C. A. T. Salama, J. P. Noel, and T.
L. Kamins, “Si/SiGe Heterostructure p-MOSFET with
Triangular Ge Channel Profiles”, Proc. International Elec.
Device Meeting (IEDM), New York, 1994, pp. 369.
[3] T. Vogelsang, F. Hofmann, H. Schäfer, L. Risch and K.
Hofmann, “Modelling and Fabrication of a P-Channel SiGe-
MOSFET with Very High Mobility and Transconductance”,
Extended Abstracts of the 1994 International Conference on
Solid State Devices and Materials, Yokohama, 1994, pp. 877-
879.
[4] V. P. Kesan, S. Subbanna, P. J. Restle, M. J. Tejwani,
J. M. Aitken, S. S. Iyer and J. A. Ott, “High Performance
0.25 µm p-MOSFETs with Silicon-Germanium Channels for
300K and 77K Operation”, Proc. International Elec. Device
Meeting (IEDM), 1991, pp. 25-28.
[5] J. Alieu, T. Skotnikii, J. L. Regoli and G. Bremond,
“Multiple SiGe Quantum Wells – Novel Channel Architecture
for 0.12µm CMOS”, Proc. of 29th European Solid-state
Device Research Conference (ESSDERC), Leuven, Belgium,
Sept 1999, pp. 292-295.
[6] Y. C. Yeo, V. Sabramanian, J. Kedzierski, P. Xuan, T.-
J. King, J. Bokor and C. Hu, “Nanoscale Ultra-Thin-Body
Silicon-on-Insulator p-MOSFET with SiGe/Si Heterostructure
Channel”, IEEE Electron Device Lett., Vol 21, 2000, pp. 161-
163.
[7] S. Kaya, Y. P. Zhao, J. R. Watling, A. Asenov, J. R.
Barker, G. Ansaripour, G. Braithwaite, T. E. Whall and E. H.
C. Parker, “Indication of Velocity Overshoot in Strained
Si0.8Ge0.2 p-Channel MOSFETs”, Semi. Sci. Tech., Vol 15,
2000, pp. 573-578.
[8] Y. P. Zhao, S. Kaya, J. R. Watling, A. Asenov, J. R.
Barker, M. Palmer, G. Braithwaite, T. E. Whall, E. H. C.
Parker, A. Waite and A. G. R. Evans, “Indication of Non-
equilibrium Transport in SiGe p-MOSFETs”, Proc. of 30th
European Solid-state Device Research Conference
(ESSDERC), Cork, Ireland, 11-13 Sep 2000,.pp. 224-227.
[9] M. J. Palmer, G. Braithwaite, T. J. Grasby, P. J.
Phillips, M. J. Prest, E. H. C. Parker, T. E. Whall, C. P. Parry,
A. M. Waite, A. G. R. Evans, S. Roy, J. R. Watling, S. Kaya
and A. Asenov, “Effective mobilities in pseudomorphic
Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect
transistors with thin silicon capping layers”, Appl. Phys.
Letters, Vol 78, 2001, pp. 1424-1426.
[10] MEDICI from Avant! Corporation,
http://www.avanticorp.com/, Fremont, CA.
[11] T. E. Whall and E. H. C. Parker, “Si/SiGe/Si pMOS
performance - alloy scattering and other considerations”, Thin
Solid Films, Vol 369, 2000, pp. 297-305.
[12] M. J. Kearney and A. I. Horrell, “The effect of alloy
scattering on the mobility of holes in a Si1-xGex quantum
well”, Semi. Sci. Tech., Vol 13, 1998, pp. 174-180.
[13] J. M. Hinckley and J. Singh, “Hole Transport Theory
in Pseudomorphic Si1-xGex Alloys Grown on Si(001)
Substrates”, Phys. Rev. B, Vol 41, 1990, pp. 2912-2926.
[14] F. M. Bufler and B. Meinerzhagen, “Hole transport in
strained Si1-xGex alloys on Si1-yGey substrates”, J. Applied
Physics, Vol 84, 1998, pp. 5597-5602.
[15] J. B. Roldan, F. Gamiz, J.A. Lopez-Villanueva and J.
E. Carceller, “Modeling Effects of Electron-Velocity
Overshoot in a MOSFET”, IEEE Trans. Electron Devices, Vol
44, 1997, pp. 841-846.
[16] K. K. Thornber, “Currrent Equations for Velocity
Overshoot”, IEEE Electron Device Lett., Vol 3, 1982, pp. 69-
71.


Enhanced velocity overshoot and transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - predictions for deep submicron devices

Enlighten

M.J. Palmer

G. Braithwaite

M.J. Prest

E.H.C. Parker

T.E. Whall

Y.P. Zhao

S. Kaya

J.R. Watling

A. Asenov

J.R. Barker

A.M. Waite

A.G.R. Evans

Crossref

Enhanced Velocity Overshoot and Transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - Predictions for Deep Submicron Devices

Electrical measurements have been carried out on Si/Si0.64 Ge0.36/Si pMOS devices and it is demonstrated that enhanced low field carrier mobilities lead to concomitant and substantial enhancements in velocity overshoot and transconductance at deep submicron channel lengths. This provides considerable motivation for incorporating SiGe into Si MOS technology

Southampton (e-Prints Soton)

Enhanced Velocity Overshoot and Transconductance in Si/Si0.64 Ge0.36/Si pMOSFETs - Predictions for Deep Submicron Devices

      Palmer, M.J. and Braithwaite, G. and Prest, M.J. and Parker, E.H.C. and Whall, T.E. and Zhao, Y.P. and Kaya, S. and Watling, J.R. and Asenov, A. and Barker, J.R. and Waite, A.M. and Evans, A.G.R. (2001) Enhanced Velocity Overshoot and Transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - Predictions for Deep Submicron Devices. In, Ryssel, H. and Wachutka, G. and Grunbacher, H., Eds. Solid State Device Research Conference, 11-13 September 2001, pages pp. 199-202, Nuremburg, Germany.      http://eprints.gla.ac.uk/3013/     Glasgow ePrints Service http://eprints.gla.ac.uk Enhanced Velocity Overshoot and Transconductance inSi/Si0.64Ge0.36/Si pMOSFETs - Predictions for Deep SubmicronDevicesM. J. Palmer, G. Braithwaite, M. J. Prest, E. H. C. Parker and T. E. WhallDept of Physics, University of Warwick, Coventry CV4 7AL, EnglandE-mail: Martin.Palmer@warwick.ac.ukY. P. Zhao, S. Kaya, J. R. Watling, A. Asenov and J. R. BarkerDevice Modelling Group, University of Glasgow, G12 8LA, ScotlandA. M. Waite and A. G. R. EvansDepartment of Electronics and Computer Science, University ofSouthampton, Highfield, Southampton, SO17 1BJ, EnglandAbstractElectrical measurements have beencarried out on Si/Si0.64Ge0.36/Si pMOSdevices and it is demonstrated thatenhanced low field carrier mobilities leadto concomitant and substantial enhance-ments in velocity overshoot andtransconductance at deep submicronchannel lengths. This provides considerablemotivation for incorporating SiGe into SiMOS technology.1. IntroductionThere is much interest in fully pseudo-morphic Si/SiGe/Si structures for Si-CMOSapplications with a major objective ofrealising symmetrical CMOS with matchingp-channel/n-channel performance [1].However, whereas performance enhance-ments are impressive - factors of two ormore at large channel lengths (>3 µm) [2],they are only modest for channel lengths ofabout 0.5 µm [3,4]. CMOS channel lengthsare now, of course, approaching 0.1 µm butthere are only a few reports on SiGedevices of this geometry. Whereas currentdrive enhancements of about a factor of twohave been demonstrated at deep submicroncompared to silicon controls, [5,6] theabsolute values of current fall short of state-of-the-art silicon. There is therefore anurgent need for more work. The presentpaper puts the disappointing results at 0.5µm into perspective and provides strongmotivation for further investigations at0.1 µm and below. Electrical measurementshave been carried out at 77K in order toaccess higher (but realistic) mobilities,which otherwise would have to be obtainedby the much more challenging route ofmaintaining materials quality in a fullyprocessed pseudomorphic device.Alternatively, high mobilities may beachieved by the use of high-germaniumcontent layers grown pseudomorphically onSiGe virtual substrates. However, theproduction of virtual substrates of sufficientquality for MOS technologies remains amajor challenge and the subject of muchstudy. At this stage their use can only beanticipated. The current investigationfollows those of Kaya et al. [7] and Zhao etal. [8], in which we reported enhancedvelocity overshoot as compared to silicon inSi/Si0.8Ge0.2/Si structures [7] and in thepresent devices [8] at 300K. It providesfurther support for the analysis given there.The previous works extend the analysisto include energy transfer and Monte-Carlosimulations. They show that the origin ofthe velocity overshoot enhancement derivesessentially from increased energy relaxationtimes in SiGe coupled with improved lowfield mobilities.2. Fabrication, Measurementand ModellingWe have measured and modelled thedrain characteristics of nominalSi/Si0.64Ge0.36/Si pMOS devices of differenteffective channel lengths 0.35 < Leff < 10µm and nominal silicon cap thicknesses2 nm ≤ tcap ≤ 8 nm. The detailed specifica-tions, fabrication and effective mobilities ofthose devices at 300K have been previouslydiscussed [9].A schematic of the MOSFET structure isshown in figure 1 and the measuredcharacteristics of a 8 nm silicon cap deviceare shown in figure 2. Using a commercial2D device simulator [10] and empiricalexpressions for the vertical and horizontalfield dependence of the carrier drift velocitywe have obtained good fits to the data, alsoshown in figure 2.3. Results and DiscussionFrom the model we have extracted theapparent saturation drift velocities, satυ~ ,given in figure 3. We note first of all thatthe long channel value of satυ~ in SiGe isless than that of silicon. In previous paperswe have argued [9,11,12] that the low fieldroom temperature mobility in theseheterostructures is limited by interfaceroughness scattering. However, it has beenshown [13,14] that alloy scatteringincreases by orders of magnitude in highhorizontal fields and this is a possibleexplanation of the low value of satυ~ in thealloy. The small value of satυ~ means thatthe current drive/transconductance at 0.5µmVDS (V)-5-4-3-2-10I DS(µA/µm)-500-400-300-200-1000VGS=-5VVGS=-4VVGS=-3VVGS=-2VVGS=-1VFigure 2. Example measured (+) andsimulated () current characteristics:SiGe, 8 nm Si cap, Leff = 0.35 µm.Si (substrate) n+ 2×1017 cm-3Si (buffer) n+ 100 nmSourcep+Drainp+Si0.64Ge0.36 10 nmSiO2 10 nmp-poly Si gateSi capLFigure 1. Schematic of the MOSFETstructureis not substantially enhanced compared tosilicon, in spite of the higher mobility [4].However, as the channel length decreases,we observe a dramatic increase in satυ~ in theSiGe devices, substantially larger than inthe silicon controls, which is attributed tovelocity overshoot.Following the analysis of Roldan et al.[15], we fit the drift velocity data to:2||~LVdxdEDSasatsatsatλυλυυ+≈+=where satυ is the velocity in a homogeneousfield, dxdE|| is the gradient of the electricfield parallel to the surface and λ andaλ are fitting parameters. Figure 4 showssatυ~ versus 1/L2 for the various devices.Using the aλ values obtained from figure 4we can predict the saturation transconduc-tance enhancement from the form [15]    ++=LLVVCLWg aDSsatDSGCmλυµµ1where CGC is the gate to channel capaci-tance and µ is the low lateral field mobilitycorresponding to the average vertical fieldin the device with VGS=-1V (to restricttransport to the SiGe channel) and VDS=-3.3V. Table 1 shows a comparison of theLeff (µm)0.1 1g m,SiGe/gm,Si0.51.01.52.02 nm cap5 nmcap8 nmcapFigure 5. Predicted enhancement ofsaturation transconductance for SiGesamples compared to silicon control.Leff (µm)1 10v sat(106cm/s)4681012~Figure 3. Fitted values of satv~ versusgate length for SiGe samples with 2nm (  ) 5 nm () and 8 nm () capsand Si control ().1/Leff2 (µm-2)0 2 4 6 8 10 12v sat(106cm/s)46810122 nmcapSi control8 nm cap5 nm cap~Figure 4. satv~ versus 1/Leff2 for SiGesamples and Si control. The 5 and 8nm data points are omitted for clarity.The trend is similar but with morescatter.Table 1. Peak low field mobility at300K [9] and 77K.Sample µ77K(cm2/Vs)µ300K(cm2/Vs)2 nm cap 569 1625 nm cap 796 2178 nm cap 1454 305Si control 322 128peak values of measured mobility at 77Kand at room temperature. The ratiosbetween the intrinsic transconductances ofthe SiGe samples and the Si control, takingaccount of the variation of CGC with verticalarchitecture, are plotted against channellength in figure 5. The model predicts up toa factor of 1.9 improvement at Leff = 0.07µm.4 ConclusionsSi0.64Ge0.36 p-channel MOSFETs operatingat 77K have been investigated in an attemptto probe a high-mobility region ofoperation. An enhanced apparent saturationvelocity at short channel lengths indicatesvelocity overshoot. The results areextrapolated to deep submicron gatelengths, predicting significant improve-ments in the transconductances of devicescontaining a SiGe channel. We expectsimilar enhancements at room temperature,especially as the low field mobilities can beimproved. Even with existing devices, arough estimate using the same extrapolationwith the room temperature analysis [8]predicts a factor of 1.4 enhancement at Leff= 0.07 µm. Notwithstanding the limitationsof the present simulation methods[7,15,16], the enhancements predicted forLeff ≤ 0.07 µm should provide considerableencouragement for those seeking tofabricate SiGe MOS devices at smallgeometries.5. References[1] T. E. Whall and E. H. C. Parker, “SiGe heterostruc-tures for FET applications” J. Phys. D. Vol 31, 1998, pp.1397–1416.[2] S. P. Voignegescu, C. A. T. Salama, J. P. Noel, and T.L. Kamins, “Si/SiGe Heterostructure p-MOSFET withTriangular Ge Channel Profiles”, Proc. International Elec.Device Meeting (IEDM), New York, 1994, pp. 369.[3] T. Vogelsang, F. Hofmann, H. Schäfer, L. Risch and K.Hofmann, “Modelling and Fabrication of a P-Channel SiGe-MOSFET with Very High Mobility and Transconductance”,Extended Abstracts of the 1994 International Conference onSolid State Devices and Materials, Yokohama, 1994, pp. 877-879.[4] V. P. Kesan, S. Subbanna, P. J. Restle, M. J. Tejwani,J. M. Aitken, S. S. Iyer and J. A. Ott, “High Performance0.25 µm p-MOSFETs with Silicon-Germanium Channels for300K and 77K Operation”, Proc. International Elec. DeviceMeeting (IEDM), 1991, pp. 25-28.[5] J. Alieu, T. Skotnikii, J. L. Regoli and G. Bremond,“Multiple SiGe Quantum Wells – Novel Channel Architecturefor 0.12µm CMOS”, Proc. of 29th European Solid-stateDevice Research Conference (ESSDERC), Leuven, Belgium,Sept 1999, pp. 292-295.[6] Y. C. Yeo, V. Sabramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor and C. Hu, “Nanoscale Ultra-Thin-BodySilicon-on-Insulator p-MOSFET with SiGe/Si HeterostructureChannel”, IEEE Electron Device Lett., Vol 21, 2000, pp. 161-163.[7] S. Kaya, Y. P. Zhao, J. R. Watling, A. Asenov, J. R.Barker, G. Ansaripour, G. Braithwaite, T. E. Whall and E. H.C. Parker, “Indication of Velocity Overshoot in StrainedSi0.8Ge0.2 p-Channel MOSFETs”, Semi. Sci. Tech., Vol 15,2000, pp. 573-578.[8] Y. P. Zhao, S. Kaya, J. R. Watling, A. Asenov, J. R.Barker, M. Palmer, G. Braithwaite, T. E. Whall, E. H. C.Parker, A. Waite and A. G. R. Evans, “Indication of Non-equilibrium Transport in SiGe p-MOSFETs”, Proc. of 30thEuropean Solid-state Device Research Conference(ESSDERC), Cork, Ireland, 11-13 Sep 2000,.pp. 224-227.[9] M. J. Palmer, G. Braithwaite, T. J. Grasby, P. J.Phillips, M. J. Prest, E. H. C. Parker, T. E. Whall, C. P. Parry,A. M. Waite, A. G. R. Evans, S. Roy, J. R. Watling, S. Kayaand A. Asenov, “Effective mobilities in pseudomorphicSi/SiGe/Si p-channel metal-oxide-semiconductor field-effecttransistors with thin silicon capping layers”, Appl. Phys.Letters, Vol 78, 2001, pp. 1424-1426.[10] MEDICI from Avant! Corporation,http://www.avanticorp.com/, Fremont, CA.[11] T. E. Whall and E. H. C. Parker, “Si/SiGe/Si pMOSperformance - alloy scattering and other considerations”, ThinSolid Films, Vol 369, 2000, pp. 297-305.[12] M. J. Kearney and A. I. Horrell, “The effect of alloyscattering on the mobility of holes in a Si1-xGex quantumwell”, Semi. Sci. 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http://eprints.gla.ac.uk/3013/1/velocity2_overshoot.pdf

Enhanced velocity overshoot and transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - predictions for deep submicron devices

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