21 research outputs found

    Development of tools for the simulation of nanometric transistors using advanced computational architectures

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    The aim of this thesis project is the study of nanoscale semiconductor devices, including new options based on new architectures and designs, for which multidimensional simulation tool based on Monte-Carlo models are going to be developed, including quantum corrections by solving the Schrödinger equation in the transverse direction to the propagation of carriers within the device. So far, our research group has developed several simulators semiconductor devices using various simulation techniques. This work is developed in collaboration with several national and international groups. It should primarily highlight the group maintains collaborations with the universities of Glasgow, Swansea and Granada and gives rise to this thesis project.The ultimate goal is to use the simulator to study various optimized, especially classical electronic devices, SOI-based and multigate, with silicon devices for sizes of under 10 nm

    Study of basic vector operations on Intel Xeon Phi and NVIDIA Tesla using OpenCL

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    The present work is an analysis of the performance of the basic vector operations AXPY, DOT and SpMV using OpenCL. The code was tested on the NVIDIA Tesla S2050 GPU and Intel Xeon Phi 3120A coprocessor. Due to the nature of the AXPY function, only two versions were implemented, the routine to be executed by the CPU and the kernel to be executed on the previously mentioned devices. It was studied how they perform for different vector’s sizes. Their results show the NVIDIA architecture better suited for the smaller vectors sizes and the Intel architecture for the larger vector’s sizes. For the DOT and SpMV functions, there are three versions implemented. The first is the CPU routine, the second one is an OpenCL kernel that uses local memory and the third one is an OpenCL kernel that only uses global memory. The kernels that use local memory are tested by varying the size of the work-group; the kernels that only uses global memory are tested by varying the arrays size. In the case of the first ones, the results show the optimum work-group size and that the NVIDIA architecture benefits from the use of local memory. For the latter kernels, the results show that larger computational loads benefits the Intel architectureThis work has been supported by FEDER funds and Xunta de Galicia under contract GRC 2014/008, and by Spanish Government (MCYT) under project TEC2010-17320 and TIN-2013-41129-PS

    Development of a novel neutron detection technique by using a boron layer coating a Charge Coupled Device

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    This article describes the design features and the first test measurements obtained during the installation of a novel high resolution 2D neutron detection technique. The technique proposed in this work consists of a boron layer (enriched in 10B) placed on a scientific Charge Coupled Device (CCD). After the nuclear reaction 10B(n,α)7Li, the CCD detects the emitted charge particles thus obtaining information on the neutron absorption position. The above-mentioned ionizing particles, with energies in the range 0.5-5.5MeV, produce a plasma effect in the CCD which is recorded as a circular spot. This characteristic circular shape, as well as the relationship observed between the spot diameter and the charge collected, is used for the event recognition, allowing the discrimination of undesirable gamma events. We present the first results recently obtained with this technique, which has the potential to perform neutron tomography investigations with a spatial resolution better than that previously achieved. Numerical simulations indicate that the spatial resolution of this technique will be about 15 μm, and the intrinsic detection efficiency for thermal neutrons will be about 3%. We compare the proposed technique with other neutron detection techniques and analyze its advantages and disadvantages.Fil: Blostein, Juan Jeronimo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Patagonia Norte; Argentina. Comisión Nacional de Energía Atómica. Centro Atómico Bariloche; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Estrada, Juan. Fermi National Accelerator Laboratory; Estados UnidosFil: Tartaglione, Aureliano. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Patagonia Norte; Argentina. Comisión Nacional de Energía Atómica. Centro Atómico Bariloche; ArgentinaFil: Sofo Haro, Miguel Francisco. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Patagonia Norte; Argentina. Comisión Nacional de Energía Atómica. Centro Atómico Bariloche; ArgentinaFil: Fernández Moroni, Guillermo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Cancelo, Gustavo Indalecio Eugenio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Patagonia Norte; Argentina. Fermi National Accelerator Laboratory; Estados Unido

    FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

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    Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures

    Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations

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    Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the Fluctuation Sensitivity Map (FSM) is used to analyse the spatial effect of the Line Edge Roughness (LER) variability in key figures-of-merit (FoM) in silicon Gate-All-Around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyse both 22 nm and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, 0.85 nm) and correlation lengths (10, 20 nm) using in-house 3D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analysed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region

    Impact of threshold voltage extraction methods on semiconductor device variability

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    This paper presents a study of the impact that several widely used threshold voltage (VT) extraction methods have on semiconductor device variability studies. The second derivative (SD), linear extrapolation (LE) and third derivative (TD) extraction techniques have been compared to the standard method used in variability, the constant current criteria (CC). To estimate the influence of these methods on the results, an ensemble of 10.7 nm gate length Si FinFETs affected by RD variability have been simulated. We have shown that variability estimators like the VT, VT and the VT shift, are heavily affected by the selected extraction methodology, with up to 30% differences in the standard deviation. We have demonstrated that being aware of which VT extraction technique has been used in a variability analysis is crucial to properly interpret the results as they may be heavily method-dependentResearch supported by the Spanish Government (TIN2013-41129-P and TIN2016-76373-P) by Xunta de Galicia and FEDER funds (GRC 2014/008) (accreditation 2016-2019, ED431G/08), by the Spanish Ministry of Economy and Competitiveness and FEDER funds (TEC2014-59402-JIN). Authors thank CESGA for the computational facilities provided. The work of G. Indalecio was supported by the Programa de Axudas á Etapa Posdoutoral da Xunta de Galicia under Grant No. 2017/077S

    Charge coupled devices for detection of coherent neutrino-nucleus scattering

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    In this article the feasibility of using charge coupled devices (CCD) to detect low-energy neutrinos through their coherent scattering with nuclei is analyzed. The detection of neutrinos through this standard model process has been elusive because of the small energy deposited in such interaction. Typical particle detectors have thresholds of a few keV, and most of the energy deposition expected from coherent scattering is well below this level. The CCD detectors discussed in this paper can operate at a threshold of approximately 30 eV, making them ideal for observing this signal. On a CCD array of 500 g located next to a power nuclear reactor the number of coherent scattering events expected is about 3000 events/year. Our results shows that a detection with a confidence level of 99% can be reached within 16 days of continuous operation; with the current 52 g detector prototype this time lapse extends to five months.Fil: Fernández Moroni, Guillermo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur; Argentina. Fermi National Accelerator Laboratory; Estados UnidosFil: Estrada, Juan. Fermi National Accelerator Laboratory; Estados UnidosFil: Paolini, Eduardo Emilio. Universidad Nacional del Sur; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; ArgentinaFil: Cancelo, Gustavo Indalecio Eugenio. Fermi National Accelerator Laboratory; Estados Unidos. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Tiffemberg, Javier. Fermi National Accelerator Laboratory; Estados UnidosFil: Molina, Jorge. Universidad Nacional de Asuncion; Paragua

    Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

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    Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON ) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF ), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device bodyThis work was supported in part by the Spanish Government under Project TIN2013-41129-P and Project TIN2016-76373-P, in part by the Xunta de Galicia and FEDER Funds under Grant GRC 2014/008, and in part by the Consellería de Cultura, Educación e Ordenación Universitaria (accreditation 2016–2019) under Grant ED431G/08. The work of Guillermo Indalecio was supported by the Programa de Axudas á Etapa Posdoutoral da Xunta de Galicia under Grant 2017/077. The work of Natalia Seoane was supported by the RyC Programme of the Spanish Ministerio de Ciencia, Innovación y Universidades under Grant RYC-2017-23312S

    Smart Readout of Nondestructive Image Sensors with Single Photon-Electron Sensitivity

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    Image sensors with nondestructive charge readout provide single-photon or single-electron sensitivity, but at the cost of long readout times. We present a smart readout technique to allow the use of these sensors in visible light and other applications that require faster readout times. The method optimizes the readout noise and time by changing the number of times pixels are read out either statically, by defining an arbitrary number of regions of interest in the array, or dynamically, depending on the charge or energy of interest in the pixel. This technique is tested in a Skipper CCD showing that it is possible to obtain deep subelectron noise, and therefore, high resolution of quantized charge, while dynamically changing the readout noise of the sensor. These faster, low noise readout techniques show that the skipper CCD is a competitive technology even where other technologies such as electron multiplier charge coupled devices, silicon photo multipliers, etc. are currently used. This technique could allow skipper CCDs to benefit new astronomical instruments, quantum imaging, exoplanet search and study, and quantum metrology.Fil: Chierchie, Fernando. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Fernández Moroni, Guillermo. Fermi National Accelerator Laboratory; Estados Unidos. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Stefanazzi, Leandro. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina. Fermi National Accelerator Laboratory; Estados UnidosFil: Paolini, Eduardo Emilio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Tiffenberg, Javier Sebastian. Fermi National Accelerator Laboratory; Estados Unidos. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Estrada, Juan. Fermi National Accelerator Laboratory; Estados UnidosFil: Cancelo, Gustavo Indalecio. Fermi National Accelerator Laboratory; Estados UnidosFil: Uemura, Sho. Universitat Tel Aviv; Israe

    Aspects on the shape dependence with energy of point-like events in high resistivity CCDs

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    Fully depleted thick CCDs have been designed for infrared astronomy, but their low read-out noise of the order of approximately 2 e− and their considerable mass of approximately 5.2gr, allows novel uses for them in low energy threshold particle detection applications, such as the CONNIE and DAMIC experiments. In both experiments, the neutrinos or WIMPS will generate e-h pairs in a volume much less than the pixel size, they will produce events like points in the output image, of less than 10 pixels. Is well understood that one of the factors that define the size of the events is the diffusion process. In this work we will demonstrate with experimental results and through simulation, that there is also a dependence of the size with the amount of charge generated by the event, due to charge repulsion effects.Fil: Fernández Moroni, Guillermo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; ArgentinaFil: Sofo Haro, Miguel Francisco. Comisión Nacional de Energía Atómica. Gerencia del Área de Energía Nuclear. Instituto Balseiro. Archivo Histórico del Centro Atómico Bariloche e Instituto Balseiro | Universidad Nacional de Cuyo. Instituto Balseiro. Archivo Histórico del Centro Atómico Bariloche e Instituto Balseiro; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Tiffemberg, Javier. Fermi National Accelerator Laboratory; Estados UnidosFil: Paolini, Eduardo Emilio. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; ArgentinaFil: Estrada, Juan. Fermi National Accelerator Laboratory; Estados UnidosFil: Bertou, Xavier Pierre Louis. Comisión Nacional de Energía Atómica. Gerencia del Área de Energía Nuclear. Instituto Balseiro. Archivo Histórico del Centro Atómico Bariloche e Instituto Balseiro | Universidad Nacional de Cuyo. Instituto Balseiro. Archivo Histórico del Centro Atómico Bariloche e Instituto Balseiro; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Cancelo, Gustavo Indalecio. Fermi National Accelerator Laboratory; Estados Unidos8th Latin American Symposium on Circuits & SystemsBarilocheArgentinaInstitute of Electrical and Electronics Engineer
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