Leveraging community assets to tackle social isolation and loneliness: a needs assessment of the London Borough of Hammersmith & Fulham

This study is an investigation of factors that influence the routine adoption and diffusion of evidence-based asset-based community development (ABCD) initiatives to combat social isolation and loneliness in the contemporary setting (using LBH&F as a case study

An investigation of performance limits of conventional and tunneling graphene-based transistors

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LArPix: Demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

We report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs). Unambiguous 3D charge readout was achieved using a custom-designed system-on-a-chip ASIC (LArPix) to uniquely instrument each pad in a pixelated array of charge-collection pads. The LArPix ASIC, manufactured in 180 nm bulk CMOS, provides 32 channels of charge-sensitive amplification with self-triggered digitization and multiplexed readout at temperatures from 80 K to 300 K. Using an 832-channel LArPix-based readout system with 3 mm spacing between pads, we demonstrated low-noise ($<$500 e$^-$ RMS equivalent noise charge) and very low-power ($<$100 $\mu$W/channel) ionization signal detection and readout. The readout was used to successfully measure the three-dimensional ionization distributions of cosmic rays passing through a LArTPC, free from the ambiguities of existing projective techniques. The system design relies on standard printed circuit board manufacturing techniques, enabling scalable and low-cost production of large-area readout systems using common commercial facilities. This demonstration overcomes a critical technical obstacle for operation of LArTPCs in high-occupancy environments, such as the near detector site of the Deep Underground Neutrino Experiment (DUNE).Comment: 19 pages, 10 figures, 1 ancillary animation. V3 includes minor revisions based on referee comment

Novel TCAD Approach for the Investigation of Charge Transport in Thick Amorphous SiO2 Insulators

A TCAD approach for the investigation of charge transport in thick amorphous silicon dioxide is presented for the first time. Thick oxides are investigated representing the best candidates for integrated galvanic insulators in future power applications. The large electric fields, such devices experience and the preexisting defects in the amorphous material, give rise to a leakage current, which leads to degradation and failure. Hence, it is crucial to have a complete understanding of the main physical mechanisms responsible for the charge transport in amorphous silicon oxide. For this reason, metal-insulator-metal structures have been experimentally characterized at different high-field stress conditions and a TCAD approach has been implemented in order to gain insight into the microscopic physical mechanisms responsible for the leakage current. In particular, the role of charge injection at contacts and charge build-up due to trapping-detrapping mechanisms in the bulk of the oxide layer has been investigated and modeled to the purpose of understanding the oxide behavior under dc- and ac-stress conditions. Numerical simulations have been compared against experiments to quantitatively validate the proposed approach

A low-field mobility model for bulk, ultrathin body SOI and double-gate n-MOSFETs with different surface and channel orientations part I: Fundamental principles

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A low-field mobility model for bulk and ultrathin-body SOI p-MOSFETs with different surface and channel orientations

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Low power discriminator for ATLAS pixel chip

The design of the front-end (FE) pixel electronics requires low power, low noise and low threshold dispersion. In this work, we propose a new architecture for the discriminator circuit. It is based on the principle of dynamic biasing and developed for the FE chip of the ATLAS pixel upgrade. This paper presents two discriminator structures where the bias current depends on the presence of a signal at the input of the discriminator. Since the activity in the FE chip is very low, the power consumption is largely reduced allowing the material reduction in the B-layer

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for the ring-oscillator based Voltage Controlled Oscillator (VCO) is fVCO = 640MHz. The last sections deal with a fabricated demonstrator that provides the option of feeding the single-ended 80MHz output clock of the PLL as a clock signal to a digital test logic block integrated on-chip. The digital logic consists of an eight bit pseudo-random binary sequence generator, an eight bit to ten bit coder and a serializer. It processes data with a speed of 160 Mbit/s. All dynamic signals are driven off-chip by custommade pseudo-LVDS drivers