Discussion on the figures of merit of identified traps located in the Si film : surface versus volume trap densities

The aim of this work is a discussion on the figures of merit of identified traps located in the depletion zone (Si film) of advanced MOSFET devices. Two methodologies to estimate the volume trap densities are investigated, one using the relationship between the surface trap density and volume trap density and a second one based on the temperature evolution at fixed frequency of the generation-recombination plateau level associated to the same trap. By comparing the volume trap densities estimated using these two methods, the results are not agreeing with each other, suggesting that these methods can no longer be used with accuracy in multigate devices. Moreover, they may lead in certain cases to results physically not correct. Even about of the volume defects, the linear evolution between the plateau and the characteristic frequency of the generation-recombination contributions associated to the same trap give us the surface trap density without any additional assumption

Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing

Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.Comment: Accepted for publication in IEEE Transactions on Nanotechnolog

Real-life assessment of chronic rhinosinusitis patients using mobile technology : The mySinusitisCoach project by EUFOREA

Background Chronic rhinosinusitis (CRS) is a chronic inflammatory disease associated with a substantial personal and socioeconomic burden. Monitoring of patient-reported outcomes by mobile technology offers the possibility to better understand real-life burden of CRS. Methods This study reports on the cross-sectional evaluation of data of 626 users of mySinusitisCoach (mSC), a mobile application for CRS patients. Patient characteristics of mSC users were analysed as well as the level of disease control based on VAS global rhinosinusitis symptom score and adapted EPOS criteria. Results The mSC cohort represents a heterogeneous group of CRS patients with a diverse pattern of major symptoms. Approximately half of patients reported nasal polyps. 47.3% of all CRS patients were uncontrolled based on evaluation of VAS global rhinosinusitis symptom score compared to 40.9% based on adapted EPOS criteria. The impact of CRS on sleep quality and daily life activities was significantly higher in uncontrolled versus well-controlled patients. Half of patients had a history of FESS (functional endoscopic sinus surgery) and reported lower symptom severity compared to patients without a history of FESS, except for patients with a history of more than 3 procedures. Patients with a history of FESS reported higher VAS levels for impaired smell. Conclusion Real-life data confirm the high disease burden in uncontrolled CRS patients, clearly impacting quality of life. Sinus surgery improves patient-reported outcomes, but not in patients with a history of more than 3 procedures. Mobile technology opens a new era of real-life monitoring, supporting the evolution of care towards precision medicine.Peer reviewe

Design, Fabrication and Characterization of Advanced Field Effect Transistors with High-Mobility Channels and Heterostructure Confinement (Ontwerp, fabricatie en karakterisatie van geavanceerde veld-effect transistoren met hoge-mobiliteitskanalen en heterostructuuropsluiting)

For many decades, the semiconductor industry has miniaturized transistors,delivering increased computing power to consumers at decreased cost. However,mere transistor downsizing does no longer provide the same improvements.One interesting option to further improve transistor characteristics is to usehigh mobility materials such as germanium and III-V materials. However,transistors have to be redesigned in order to fully benefit from these alternativematerials. This thesis shows that Quantum Well based transistors can bequite suited for this, since they confine the charge carriers to the high-mobilitymaterial using a heterostructure. One particular structure, the SiGe Implant-Free Quantum Well pFET was designed and fabricated using industry-scaledinfrastructure. Electrical testing showed remarkable short-channel performanceand prototypes were found to be competitive with a state-of-the-art planarstrained-silicon technology. High mobility channel, providing high drive current,and heterostructure confinement, providing good short-channel control make aninteresting combination for future technology nodes. Starting with an investigation of a bulk germanium FET technology, the fabrication ofshallow junctions in germanium substrates was investigated. Both boron and galliumwere found to be suitable p-type dopants, delivering high electrical activation up to4 x1020cm-3 while dopant diffusion remains negligible (under certain conditions).Considering n-type dopants, arsenic was studied, focussing on millisecond laserannealing in an attempt to reduce the concentration-enhanced diffusion. While theactive dopant concentration was rather high, significant diffusion was still observed. Following this experimental work, a Monte Carlo simulator was calibrated to enableTCAD simulations of ion implants into Ge substrates. Simulated as-implanted profilesfor B, P, Ga and As showed good agreement with experimental data. Using thiscalibrated MC simulator, the ion implant steps for a scaled 70-nm Ge pMOSFETtechnology were designed. Fabricated transistors were found to outperform the ITRSrequirements for the corresponding technology node. A commercial TCAD simulatorwas also extended to allow electrical simulations of Ge pMOSFETs. Specifically,models for carrier mobility and generation/recombination processes were calibratedusing experimental data. Electrical simulations of Ge pMOSFETs were found to bein good agreement with electrical measurements. Typical performance metrics (ION,IOFF , DIBL etc.) were within 5-10% of experimental values. Complementingexperimental work, this TCAD combination allows optimizing and predicting theperformance of new, scaled germanium-based devices.However, it seems unlikely that a planar bulk germanium technology would bewell suitedfor future technology nodes, because of drain-to-bulk junction leakage.Addressing this issue, another strategy was followed to integrate high-mobility channelmaterials such as germanium into future technology nodes. A class of transistors wasintroduced, which only uses the high-mobility material in the transistor channel. Theyare designed in such a way that the charge carriers are confined to a Quantum Well bymeans of heterostructure confinement. In the Si/SiGe material system, the SiGe Implant-Free Quantum Well (IFQW)transistor was developed and TCAD simulations predicted excellent short channelcontrol down to 16 nm gate lengths, markedly better than for equivalent bulk siliconpFETs. In InGaAs-based IFQW nFET was also designed, showing good short channelcontrol at a gate length of 10 nm. Finally, the SiGe Implant-Free Quantum Well transistors were fabricated usingindustry-scaled infrastructure. First-generation SiGe IFQW pFETs with raised sourceand drain were electrically analyzed. Devices with gate lengths down to 30 nm showedexcellent short channel control with DIBL and SS values of 126 mV/V and 80mV/dec respectively. Compared to Si control pFETs, a 50% higher drive currentwas obtained. Integrating embedded SiGe source drain stressors into this IFQW pFETarchitecture, second-generation IFQW pFETs were fabricated. These prototypes werefound to be competitive with a 32-nm node state-of-the-art strained-silicon technology,combining a high saturation drive current of 1 mA/µm, maintaining the improved shortchannel control. Considering that there is still significant room for further improvementof this IFQW pFET, this comparison suggests that it should be considered a viabletechnology option for upcoming technology nodes.nrpages: 169status: publishe

High mobility and quantum well transistors: design and TCAD simulation

For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Quantum Well pFET – is discussed. Electrical testing shows remarkable short-channel performance and prototypes are found to be competitive with a state-of-the-art planar strained-silicon technology. High mobility channels, providing high drive current, and heterostructure confinement, providing good short-channel control, make a promising combination for future technology nodes

Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities

International audienc

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

peer reviewedWe report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform

Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs

International audienc

Numerical analysis of the new implant-free quantum-well CMOS: DualLogic approach

The research into alternative channel materials to improve CMOS performance is a rapidly growing area of research. III–V and Ge based MOSFETs offer attractive possibilities for a high performance and low power circuit implementation. Here, we report a global performance analysis of future DualLogic CMOS based on the new, Implant-FreeQuantum-Well device architecture for both III–V nMOSFETs and Ge pMOSFETs. The III–V nMOSFETs are optimised to achieve low leakage, high performance and its performance is evaluated using ensemble Monte Carlo simulations. A similar approach is adopted for the Ge pMOSFETs. In addition, the impact of the interface states density on the output characteristics is also studied. Finally, the timing performance of the DualLogic CMOS is evaluated using mixed mode TCAD and circuit simulations