Design, Fabrication and Characterization of Advanced Field Effect Transistors with High-Mobility Channels and Heterostructure Confinement (Ontwerp, fabricatie en karakterisatie van geavanceerde veld-effect transistoren met hoge-mobiliteitskanalen en heterostructuuropsluiting)

Abstract

For many decades, the semiconductor industry has miniaturized transistors,delivering increased computing power to consumers at decreased cost. However,mere transistor downsizing does no longer provide the same improvements.One interesting option to further improve transistor characteristics is to usehigh mobility materials such as germanium and III-V materials. However,transistors have to be redesigned in order to fully benefit from these alternativematerials. This thesis shows that Quantum Well based transistors can bequite suited for this, since they confine the charge carriers to the high-mobilitymaterial using a heterostructure. One particular structure, the SiGe Implant-Free Quantum Well pFET was designed and fabricated using industry-scaledinfrastructure. Electrical testing showed remarkable short-channel performanceand prototypes were found to be competitive with a state-of-the-art planarstrained-silicon technology. High mobility channel, providing high drive current,and heterostructure confinement, providing good short-channel control make aninteresting combination for future technology nodes. Starting with an investigation of a bulk germanium FET technology, the fabrication ofshallow junctions in germanium substrates was investigated. Both boron and galliumwere found to be suitable p-type dopants, delivering high electrical activation up to4 x1020cm-3 while dopant diffusion remains negligible (under certain conditions).Considering n-type dopants, arsenic was studied, focussing on millisecond laserannealing in an attempt to reduce the concentration-enhanced diffusion. While theactive dopant concentration was rather high, significant diffusion was still observed. Following this experimental work, a Monte Carlo simulator was calibrated to enableTCAD simulations of ion implants into Ge substrates. Simulated as-implanted profilesfor B, P, Ga and As showed good agreement with experimental data. Using thiscalibrated MC simulator, the ion implant steps for a scaled 70-nm Ge pMOSFETtechnology were designed. Fabricated transistors were found to outperform the ITRSrequirements for the corresponding technology node. A commercial TCAD simulatorwas also extended to allow electrical simulations of Ge pMOSFETs. Specifically,models for carrier mobility and generation/recombination processes were calibratedusing experimental data. Electrical simulations of Ge pMOSFETs were found to bein good agreement with electrical measurements. Typical performance metrics (ION,IOFF , DIBL etc.) were within 5-10% of experimental values. Complementingexperimental work, this TCAD combination allows optimizing and predicting theperformance of new, scaled germanium-based devices.However, it seems unlikely that a planar bulk germanium technology would bewell suitedfor future technology nodes, because of drain-to-bulk junction leakage.Addressing this issue, another strategy was followed to integrate high-mobility channelmaterials such as germanium into future technology nodes. A class of transistors wasintroduced, which only uses the high-mobility material in the transistor channel. Theyare designed in such a way that the charge carriers are confined to a Quantum Well bymeans of heterostructure confinement. In the Si/SiGe material system, the SiGe Implant-Free Quantum Well (IFQW)transistor was developed and TCAD simulations predicted excellent short channelcontrol down to 16 nm gate lengths, markedly better than for equivalent bulk siliconpFETs. In InGaAs-based IFQW nFET was also designed, showing good short channelcontrol at a gate length of 10 nm. Finally, the SiGe Implant-Free Quantum Well transistors were fabricated usingindustry-scaled infrastructure. First-generation SiGe IFQW pFETs with raised sourceand drain were electrically analyzed. Devices with gate lengths down to 30 nm showedexcellent short channel control with DIBL and SS values of 126 mV/V and 80mV/dec respectively. Compared to Si control pFETs, a 50% higher drive currentwas obtained. Integrating embedded SiGe source drain stressors into this IFQW pFETarchitecture, second-generation IFQW pFETs were fabricated. These prototypes werefound to be competitive with a 32-nm node state-of-the-art strained-silicon technology,combining a high saturation drive current of 1 mA/µm, maintaining the improved shortchannel control. Considering that there is still significant room for further improvementof this IFQW pFET, this comparison suggests that it should be considered a viabletechnology option for upcoming technology nodes.nrpages: 169status: publishe