Design of Digital Advanced Systems Based on Programmable System on Chip

This chapter fills up an advanced analysis of the state-of-the-art design in programmable SoC systems, giving a critical overall vision for every designer to implement real time operating systems and concurrent processing. The content of the chapter is divided in the next four main sections. First the evolution timeline of FPGA based systems is covered from its beginning until the last AP SoC chips. They are complex devices and it is necessary to have a well-known understanding to utilise them in the more efficient form possible. The more important advance digital systems structures and architectures are described. The embedded AP SoCs are analysed and main design methodologies are covered, focusing in hardware and co-design strategies. In this section is described the development of a real open source application that covers the fundamental parts in the design of a SoC system, ranging from the hardware development until the software design involving the embedded operating system and the user interface application. Finally, the system described in the last section is tested in a real scientific experiment and the results are evaluated

Extraction of thermal characteristics of surrounding geological layers of a geothermal heat exchanger by 3D numerical simulations

Ground thermal conductivity and borehole thermal resistance are key parameters for the design of closed Ground-Source Heat Pump (GSHP) systems. The standard method to determine these parameters is the Thermal Response Test (TRT). This test analyses the ground thermal response to a constant heat power injection or extraction by measuring inlet and outlet temperatures of the fluid at the top of the borehole heat exchanger. These data are commonly evaluated by models considering the ground being homogeneous and isotropic. This approach estimates an effective ground thermal conductivity representing an average of the thermal conductivity of the different layers crossed by perforation. In order to obtain a thermal conductivity profile of the ground as a function of depth, two additional inputs are needed; first, a measurement of the borehole temperature profile and, second, an analysis procedure taking into account ground is not homogeneous. This work presents an analysis procedure, complementing the standard TRT analysis, estimating the thermal conductivity profile from a temperature profile along the borehole during the test. The analysis procedure is implemented by a 3D Finite Element Model (FEM) in which depth depending thermal conductivity of the subsoil is estimated by fitting simulation results with experimental data. The methodology is evaluated by the recorded temperature profiles throughout a TRT in a BHE (Borehole Heat Exchanger) monitored facility, which allowed the detection of a highly conductive layer at 25 meters depth. © 2015 Elsevier Ltd. All rights reserved.This work has been supported by the EIT Climate-KIC, a body of the European Union inside the PhD Programme of TBE Platform.Aranzabal, N.; Martos, J.; Montero Reguera, ÁE.; Monreal Mengual, L.; Soret, J.; Torres, J.; García Olcina, R. (2016). Extraction of thermal characteristics of surrounding geological layers of a geothermal heat exchanger by 3D numerical simulations. Applied Thermal Engineering. 99:92-102. doi:10.1016/j.applthermaleng.2015.12.109921029

Novel Wireless Sensor System for Dynamic Characterization of Borehole Heat Exchangers

The design and field test of a novel sensor system based in autonomous wireless sensors to measure the temperature of the heat transfer fluid along a borehole heat exchanger (BHE) is presented. The system, by means of two specials valves, inserts and extracts miniaturized wireless sensors inside the pipes of the borehole, which are carried by the thermal fluid. Each sensor is embedded in a small sphere of just 25 mm diameter and 8 gr weight, containing a transceiver, a microcontroller, a temperature sensor and a power supply. A wireless data processing unit transmits to the sensors the acquisition configuration before the measurements, and also downloads the temperature data measured by the sensor along its way through the BHE U-tube. This sensor system is intended to improve the conventional thermal response test (TRT) and it allows the collection of information about the thermal characteristics of the geological structure of subsurface and its influence in borehole thermal behaviour, which in turn, facilitates the implementation of TRTs in a more cost-effective and reliable way

Microprocesador MicroBlaze de Xilinx

Material docente perteneciente a la asignatura Sistemas Integrados que se imparte en el Máster Oficial de Ingeniería Electrónica de la ETSE-UV.MicroBlaze es un bloque microprocesador “software” diseñado para su implementación en FPGAs de Xilinx. Este elemento presenta un juego de instrucciones reducido (RISC), acceso a instrucciones y datos de forma independiente (Harvard). En este sentido, se profundiza en las características de este microprocesador y se definen las posibilidades que posee para interconectar diferentes periféricos y módulos funcionales. Este material docente incorpora en este diseño con MicroBlaze se utiliza un timer para implementar un contador y, adicionalmente, a aprender como funciona el sistema de interrupciones en MicroBlaze. También se proporciona una práctica guiada que consiste en integrar un core como periférico de MicroBlaze.MicroBlaze is a "software" microprocessor block designed for implementation in Xilinx FPGAs. This element presents a set of reduced instructions (RISC), access to instructions and data independently (Harvard). In this sense, the characteristics of this microprocessor are deepened and the possibilities it has to interconnect different peripherals and functional modules are defined. This teaching material incorporated in this design with MicroBlaze uses a timer to implement a counter and, additionally, to learn how the system of interrupts in MicroBlaze works. A guided practice consisting of integrating a core as a MicroBlaze peripheral is also provided

RF Acquisition System Based on μTCA for Testing of High-Gradient Acceleration Cavities

The radio frequency (RF) laboratory hosted in the Corpuscular Physics Institute (IFIC) of the University of Valencia is designed to house a high-power and high-repetition-rate facility to test normal conduction RF accelerator cavities in the S-Band (2.9985 GHz) in order to perform R&D activities related to particle accelerator cavities. The system, which manages the entire process of RF signal generation, data acquisition and closed-loop control of the laboratory, is currently based on a modular and compact PXI platform system. This contribution details the development of a platform with similar features, but which is based on open architecture standards at both the hardware and software level. For this purpose, a complete system based on the μTCA platform has been developed. This new system must be able to work with accelerator cavities at other operating frequencies, such as 750 MHz, as well as to explore different options at firmware and software levels based on open-source codes

Arquitectura de las FPGAs de Xilinx

Las FPGAs se caracterizan por poseer recursos lógicos, constituidos por bloques lógicos configurables, repartidos por todo el circuito y por recursos de interconexión formados por líneas de interconexión y conexiones configurables. Además de profundizar en esta arquitectura, se presentan y definen las características principales de las FPGAs: gran capacidad de integración, arquitectura flexible que se adapta fácilmente a cada aplicación, poseen recursos específicos para la realización de circuitos aritméticos, presentan recursos lógicos específicos para realizar unidades de memoria internas y programación por descripción hardware, capacidad de trabajar varias aplicaciones en paralelo. Así mismo, la parte teórica viene reforzada con dos prácticas aplicadas mediante la que se implementa una comunicación puerto serie en MicroBlaze.FPGAs are characterized by having logical resources, constituted by configurable logic blocks, distributed throughout the circuit and by interconnection resources formed by interconnection lines and configurable connections. In addition to deepening this architecture, the main features of the FPGAs are presented and defined: great integration capacity, flexible architecture that adapts easily to each application, they have specific resources for the realization of arithmetic circuits, they present specific logical resources to realize units of internal memory and programming by hardware description, ability to work several applications in parallel. Likewise, the theoretical part is reinforced with two applied practices through which a serial port communication is implemented in MicroBlaze

Timing results using an FPGA-based TDC with large arrays of 144 SiPMs

Silicon photomultipliers (SiPMs) have become an alternative to traditional tubes due to several features. However, their implementation to form large arrays is still a challenge especially due to their relatively high intrinsic noise, depending on the chosen readout. In this contribution, two modules composed of SiPMs with an area of roughly mm mm are used in coincidence. Coincidence resolving time (CRT) results with a field-programmable gate array, in combination with a time to digital converter, are shown as a function of both the sensor bias voltage and the digitizer threshold. The dependence of the CRT on the sensor matrix temperature, the amount of SiPM active area and the crystal type is also analyzed. Measurements carried out with a crystal array of 2 mm pixel size and 10 mm height have shown time resolutions for the entire 288 SiPM two-detector set-up as good as 800 ps full width at half maximum (FWHM).This work was supported in part by the University of Valencia and the Institute for Instrumentation and Molecular Imaging.Aguilar, A.; González Martínez, AJ.; Torres, J.; García Olcina, R.; Martos, J.; Soret, J.; Conde Castellanos, PE.... (2015). Timing results using an FPGA-based TDC with large arrays of 144 SiPMs. IEEE Transactions on Nuclear Science. 62(1):12-18. doi:10.1109/TNS.2014.2359078S121862

Herramienta de diseño para MicroBlaze: EDK

Material docente perteneciente a la asignatura Sistemas Integrados que se imparte en el Máster Oficial de Ingeniería Electrónica de la ETSE-UV.Presentación de la plataforma EDK, la herramienta de diseño hardware que se emplea para gestionar los sistemas integrados de Xilinx. EDK permite la integración de los componentes hardware del Sistema Integrado y del código software para que los mismos actúen. También permite la Simulación, Depuración y Programación de todo el diseño. El material docente contiene un ejercicio práctico basado en crear una aplicación básica que nos permita acceder a cualquier periférico que se desee controlar con MicroBlaze. Para ello, se emplea XPS para generar la aplicación software, creando el archivo de programación a verificar de manera hardware. Así mismo, se propone el empleo un linker script simple que permita automatizar todo el proceso.Presentation of the EDK platform, the hardware design tool used to manage integrated Xilinx systems. EDK allows the integration of the hardware components of the Integrated System and the software code so that they act. It also allows the Simulation, Debugging and Programming of the entire design. The teaching material contains a practical exercise based on creating a basic application that allows us to access any peripheral you wish to control with MicroBlaze. To do this, XPS is used to generate the software application, creating the programming file to be verified in a hardware way. Likewise, the use of a simple linker script that allows automating the entire process is proposed