SAMIE-LSQ: set-associative multiple-instruction entry load/store queue

The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processor hotspots. This paper presents a highly banked, set-associative, multiple-instruction entry LSQ (SAMIE-LSQ,) that achieves high performance with small energy requirements. The SAMIE-LSQ classifies the memory instructions (loads and stores) based on the address to be accessed, and groups those instructions accessing the same cache line in the same entry. Our approach relies on the fact that many in-flight memory instructions access the same cache lines. Each SAMIE-LSQ entry has space for several memory instructions accessing the same cache line. This arrangement has a number of advantages. First, it significantly reduces the address comparison activity needed for memory disambiguation since there are less addresses to be compared. It also reduces the activity in the data TLB, the cache tag and cache data arrays. This is achieved by caching the cache line location and address translation in the corresponding SAMIE-LSQ entry once the access of one of the instructions in an entry is performed, so instructions that share an entry can reuse the translation, avoid the tag check and get the data directly from the concrete cache way without checking the others. Besides, the delay of the proposed scheme is lower than that required by a conventional LSQ. We show that the SAMIE-LSQ saves 82% dynamic energy for the load/store queue, 42% for the LI data cache and 73% for the data TLB, with a negligible impact on performance (0.6%)Peer ReviewedPostprint (published version

Low-complexity distributed issue queue

As technology evolves, power density significantly increases and cooling systems become more complex and expensive. The issue logic is one of the processor hotspots and, at the same time, its latency is crucial for the processor performance. We present a low-complexity FP issue logic (MB/spl I.bar/distr) that achieves high performance with small energy requirements. The MB/spl I.bar/distr scheme is based on classifying instructions and dispatching them into a set of queues depending on their data dependences. These instructions are selected for issuing based on an estimation of when their operands will be available, so the conventional wakeup activity is not required. Additionally, the functional units are distributed across the different queues. The energy required by the proposed scheme is substantially lower than that required by a conventional issue design, even if the latter has the ability of waking-up only unready operands. MB/spl I.bar/distr scheme reduces the energy-delay product by 35% and the energy-delay product by 18% with respect to a state-of-the-art approach.Peer ReviewedPostprint (published version

Inherently workload-balanced clustered microarchitecture

The performance of clustered microarchitectures relies on steering schemes that try to find the best trade-off between workload balance and inter-cluster communication penalties. In previously proposed clustered processors, reducing communication penalties and balancing the workload are opposite targets, since improving one usually implies a detriment in the other. In this paper we propose a new clustered microarchitecture that can minimize communication penalties without compromising workload balance. The key idea is to arrange the clusters in a ring topology in such a way that results of one cluster can be forwarded to the neighbor cluster with a very short latency. In this way, minimizing communication penalties is favored when the producer of a value and its consumer are placed in adjacent clusters, which also favors workload balance. The proposed microarchitecture is shown to outperform a state-of-the-art clustered processor. For instance, for an 8-cluster configuration and just one fully pipelined unidirectional bus, 15% speedup is achieved on average for FP programs.Peer ReviewedPostprint (published version

"Proctoeces maculatus" "(Trematoda: Digenea)", paràsit del musclo "Mytilus edulis": Estructura, desenvolupament i ultrastructura de la cercària

About 1 % of the mussel beds of the Galician coast are affected by the so called «orange sickness», a disease detected for the first time by COLE (1935) and caused by Proctoeces maculatus (Trematoda: Digenea), whose sporocysts, approximately one thousand in number, infect different organs of the host, amongst the most important of which are the pallium and the gonads. The sporocist has the shape of an oval bag in which sporocysts in formation as well as cercariae in different developping phases dwell; some morphological differences between the latter and the former appear already during the early phases. The acetabulum of the cercaria differenciates itself as a spherical cavity whose wall presents muscular fibres in radial and circular directions. At the same time, the cercaria's own teguments are being developped and the tegumentary cover that surrounds it degenerates during development, which originated in the sporocyst's wall. Cells of a connective tissue nature form the parenchyma of the cercaria, which present very well defined boundaries and scarcity of intercellular matter

Robust eye tracking based on multiple corneal reflections for clinical applications

Postprint (published version

Nous criteris milloren el diagnòstic del càncer pleural

Per facilitar el diagnòstic d'un càncer pleural els metges duen a terme una exploració a la cavitat toràcica, un mètode anomenat toracoscòpia. Investigadors de la UAB i de l'Hospital Vall d'Hebron han observat que, malgrat tot, aquesta tècnica invasiva ha estat innecessària en molts casos.Para facilitar el diagnóstico de un cáncer pleural los médicos realizan una exploración en la cavidad torácica, este método se llama toracoscopia. Sin embargo, investigadores de la UAB y del Hospital Vall d'Hebron han observado que esta técnica invasiva muchas veces ha sido innecesaria

Morocco, occupying power of Western Sahara: some notes about Spain’s foreign legal policy, the role of the Spanish doctrine and the rule of law in international relations

There is no doubt that, for the past 47 years, Morocco has been the occupying power over most of the territory of Western Sahara. However, a brief analysis of institutional and relational practice shows that, on the one hand, both the main international organisations concerned — the United Nations and the European Union — and the Western powers — the United States, France, etc. — maintain a certain degree of indeterminacy regarding the legal regime that should be applied to Morocco, in accordance with the rules of international law in force, particularly with respect to international humanitarian law. On the other hand, an analysis of the practice shows the lack of response or reaction from the United Nations, the European Union and Western powers to the North African state’s flagrant and prolonged non-compliance with these norms. More specifically, Spain, the former administering power of Western Sahara, takes little interest in Morocco’s compliance with these norms. The Spanish government has even recently stated that it supports the annexationist theses defended by the Moroccan monarchy. Given this situation, Spain’s international law doctrine could adopt a more active and organised role in defending compliance with international law in relation to the Western Sahara conflict, and in general in the development of Spain’s foreign policy as a whole. In short, in defending the validity of rule of law in international relations.This work forms part of the research activities carried out within the framework of the research project, awarded by the Ministry of Science and Innovation, “The respect for human rights and the external activity of Spanish companies: challenges and responses from international law” (PID2019-107311RB-I00); and the Jean Monnet Centre of Excellence “Inter-University for European Studies of the University of Alicante: The European Union and the Mediterranean” (619838-EPP-1-2020-ES-EPPJMO-CoE)

Modelling probabilistic cache representativeness in the presence of arbitrary access patterns

Measurement-Based Probabilistic Timing Analysis (MBPTA) is a promising powerful industry-friendly method to derive worst-case execution time (WCET) estimates as needed for critical real-time embedded systems. MBPTA performs several (R) runs of the program on the target platform collecting the execution times in each run. MBPTA builds a probabilistic representativeness argument on whether those events with high impact on execution time, such as cache misses, arise on the runs made at analysis time so that their impact on execution time is captured. So far only events occurring in cache memories have been shown to challenge providing such representativeness argument. In this context, this paper introduces a representativeness validation method (RVS) to assess the probabilistic representativeness of MBPTA’s execution time observations in terms of cache behaviour. RVS resorts to cache simulation to predict worst-case miss scenarios that can appear during the deployment phase. RVS also constructs a probabilistic Worst-Case Miss Count curve based on the miss-counts captured in the R runs. If that curve upperbounds the impact of the predicted cache worst-case scenarios, R is deemed as a sufficient number of runs for which pWCET estimates can be reliably derived. Otherwise, the user is requested to perform more runs until all cache scenarios of interest are captured.Peer ReviewedPostprint (author's final draft