114 research outputs found
CARS: A New Code Generation Framework for Clustered ILP Processors
Get PDFClustered ILP processors are characterized by a large number of
non-centralized on-chip resources grouped into clusters. Traditional code
generation schemes for these processors consist of multiple phases for
cluster assignment, register allocation and instruction scheduling.
Most of these approaches need additional re-scheduling phases because they
often do not impose finite resource constraints in all phases of code
generation. These phase-ordered solutions have several drawbacks,
resulting in the generation of poor performance code. Moreover, the
iterative/back-tracking algorithms used in some of these schemes have
large running times. In this report we present CARS, a code generation
framework for Clustered ILP processors, which combines the cluster
assignment, register allocation, and instruction scheduling phases into a
single code generation phase, thereby eliminating the problems associated
with phase-ordered solutions. The CARS algorithm explicitly takes into
account all the resource constraints at each cluster scheduling step to
reduce spilling and to avoid iterative re-scheduling steps. We also
present a new on-the-fly register allocation scheme developed for CARS.
We describe an implementation of the proposed code generation framework and
the results of a performance evaluation study using the SPEC95/2000 and
MediaBench benchmarks.
(Also cross-referenced as UMIACS-TR-2000-55
Machine learning of symbolic compositional rules with genetic programming: dissonance treatment in Palestrina
Get PDFWe describe a method for automatically extracting symbolic compositional rules from music corpora. Resulting rules are expressed by a combination of logic and numeric relations, and they can therefore be studied by humans. These rules can also be used for algorithmic composition, where they can be combined with each other and with manually programmed rules. We chose genetic programming (GP) as our machine learning technique, because it is capable of learning formulas consisting of both logic and numeric relations. GP was never used for this purpose to our knowledge. We therefore investigate a well understood case in this study: dissonance treatment in Palestrina’s music. We label dissonances with a custom algorithm, automatically cluster melodic fragments with labelled dissonances into different dissonance categories (passing tone, suspension etc.) with the DBSCAN algorithm, and then learn rules describing the dissonance treatment of each category with GP. Learning is based on the requirement that rules must be broad enough to cover positive examples, but narrow enough to exclude negative examples. Dissonances from a given category are used as positive examples, while dissonances from other categories, melodic fragments without dissonances, purely random melodic fragments, and slight random transformations of positive examples, are used as negative examples
Coordinated parallelizing compiler optimizations and high-level synthesis
Full text linkWe present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a presynthesis phase and during scheduling, with the objective of optimizing the results of synthesis and reducing the impact of control flow constructs on the quality of results. We first apply a set of source level presynthesis transformations that include common sub-expression elimination (CSE), copy propagation, dead code elimination and loop-invariant code motion, along with more coarse-level code restructuring transformations such as loop unrolling. We then explore scheduling techniques that use a set of aggressive speculative code motions to maximally parallelize the design by re-ordering, speculating and sometimes even duplicating operations in the design. In particular, we present a new technique called "Dynamic CSE" that dynamically coordinates CSE and code motions such as speculation and conditional speculation during scheduling. We implemented our parallelizing high-level synthesis in the SPARK framework. This framework takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. Our results from computationally expensive portions of three moderately complex design targets, namely, MPEG-1, MPEG-2 and the GIMP image processing too], validate the utility of our approach to the behavioral synthesis of designs with complex control flows
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