Effect of the plasticizer on permeability, mechanical resistance and thermal behaviour of composite coating films

Thin layer deposit of a composite material on solid particle surfaces used in the food industry aims to ensure the protection of food powder against aggressive environments such as amoist atmosphere. The layer, having a thickness of a few fractions of millimetre, must have certain physico-chemical properties: it must be compatible with the product, itmust be impermeable to water and oxygen, itmust have goodmechanical strength and good adhesion to the surface of the coated powder. Furthermore the layer must fulfil the regulatory requirements for food ingredients. Film properties like continuity, permeability, and mechanical resistance depend on the choice of the excipients included in the formulation and the operating conditions which can modify the constraints generated at the interface film-powder. As a consequence, the scientific issue consists of combining the local phenomena happening at amicroscopic level on the surface of the particle with the processing technology and the process parameters. In a first step, the attention is focussed on the film and its formulation. For this step, films are prepared separately and they are dried under very smooth conditions. Test samples are taken from the formed composite films and contain hydroxypropyl methylcellulose asmatrix (67% of driedmaterial),micronised stearic acid as hydrophobic filler (20% of driedmaterial) and a plasticizer (13% of driedmaterial). The filmformation procedure and the testmethod are described in detail. The effect of the type of plasticizer (different grades of PEG) onmechanical, thermal and permeability properties of the coating film is studied. The results show that PEG with higher molecular rate provides a better plasticizing effect for the film but increases the water vapour permeability of the film

Méthodologie basée sur des membranes pour la gestion de la reconfiguration dynamique dans les systèmes embarqués parallèles

National audienceLa reconfiguration partielle et dynamique donne une nouvelle dimension pertinente et efficace à la conception des systèmes embarqués parallèles. Toutefois, en raison de la complexité de ces systèmes, assurer la cohérence et la gestion du parallélisme lors de l'exécution reste un défi majeur. Ainsi, des modèles d'architectures et des méthodologies de conception assistée sont nécessaires pour permettre la gestion efficace de la reconfiguration matérielle. Notre approche est inspirée des modèles, à base de composants, bien connus dans le monde du logiciel. Le modèle que l'on propose est basé sur des membranes enveloppant les composants du système. L'objectif est d'améliorer la productivité de conception et d'assurer la cohérence de la gestion des changements de composants virtuels réutilisables (IPs) ainsi que le changement de contexte. Ces membranes sont distribuées et optimisées dans le but de concevoir des systèmes autoadaptatifs

NoC Design Flow for TDMA and QoS Management in a GALS Context

International audienceThis paper proposes a new approach dealing with the tedious problem of NoC guaranteed traffics according to GALS constraints impelled by the upcoming large System-on-Chips with multiclock domains. Our solution has been designed to adjust a tradeoff between synchronous and clockless asynchronous techniques. By means of smart interfaces between synchronous sub-NoCs, Quality-of-Service (QoS) for guaranteed traffic is assured over the entire chip despite clock heterogeneity. This methodology can be easily integrated in the usual NoC design flow as an extension to traditional NoC synchronous design flows. We present real implementation obtained with our tool for a 4G telecom scheme

Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance

International audienceAsymmetric coherency is a new optimisation method for coherency policies to support non-uniform work- loads in multicore processors. Asymmetric coherency assists in load balancing a workload and this is applica- ble to SoC multicores where the applications are not evenly spread among the processors and customization of the coherency is possible. Asymmetric coherency is a policy change, and consequently our designs re- quire little or no additional hardware over an existing system. We explore two different types of asymmetric coherency policies. Our bus based asymmetric coherency policy, generated a 60% coherency cost reduction (reduction of latencies due to coherency messages) for non-shared data. Our directory based asymmetric co- herency policy, showed up to a 5.8% execution time improvement and up to a 22% improvement in average memory latency for the parallel benchmarks Sha, using a statically allocated asymmetry. Dynamically allo- cated asymmetry was found to generate further improvements in access latency, increasing the effectiveness of asymmetric coherency by up to 73.8% when compared to the static asymmetric solution

Lightweight reconfiguration security services for AXI-based MPSoCs

International audienceNowadays, security is a key constraint in MPSoC development as many critical and secret information can be stored and manipulated within these systems. Addressing the protection issue in an efficient way is challenging as information can leak from many points. However one strategic component of a bus-based MPSoC is the communication architecture as all information that an attacker could try to extract or modify would be visible on the bus. Thus monitoring and controlling communications allows an efficient protection of the whole system. Attacks can be detected and discarded before system corruption. In this work, we propose a lightweight solution to dynamically update hardware firewall enhancements which secure data exchanges in a bus-based MPSoC. It provides a standalone security solution for AXI-based embedded systems where no user intervention is required for security mechanisms update. An FPGA implementation demonstrates an area overhead of around 11% for the adaptive version of the hardware firewall compared to the static one

Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems

International audiencePartial and dynamic reconfiguration provides a relevant new dimension to design efficient parallel embedded systems. However, due to the encasing complexity of such systems, ensuring the consistency and parallelism management at runtime is still a key challenge. So architecture models and design methodology are required to allow for efficient component reuse and hardware reconfiguration management.This paper presents a distributed persistence management model and its implementation for reconfigurable multiprocessor systems on dynamically reconfigurable circuits. The proposed approach is inspired from the well-known component based models used in software applications development. Our model is based on membranes wrapping the systems components. The objective is to improve design productivity and ensure consistency by managing context switching and storage using modular distributed hardware controllers. These membranes are distributed and optimized with the aim to design self-adaptive systems by allowing dynamic changes in parallelism degree and contexts migration. Simulation and synthesis results are given to show performances and effectiveness of our methodology

Design of multimedia processor based on metric computation

Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility

Processor Enhancements for Media Streaming Applications

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodolog

Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems

In this paper we present a hierarchy of bitstreams repositories for FPGA-based networked and partially reconfigurable systems. These systems target embedded systems with very scarce hardware resources taking advantage of dynamic, specific and optimized architectures. Based on FPGA integrated circuits, they require a single FPGA with a network controller and less external memories to store reconfiguration software, bitstreams and buffer pools used by today's standard communication protocols. Our measures, based on a real implementation, show that our repository hierarchy is functional and can download bitstreams with a reconfiguration speed ten times faster than known solutions