74 research outputs found
High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates
Mathematical analysis and optimization of a carrier tracking loop are presented. Due to fast changing of the carrier frequency in some satellite systems, such as Low Earth Orbit (LEO) or Global Positioning System (GPS), or some planes like Unmanned Aerial Vehicles (UAVs), high dynamic tracking loops play a very important role. In this paper an optimized tracking loop consisting of a third-order Phase Locked Loop (PLL) assisted by a second-order Frequency Locked Loop (FLL) for UAVs is proposed and discussed. Based on this structure an optimal loop has been designed. The main advantages of this approach are the reduction of the computation complexity and smaller phase error. The paper shows the simulation results, comparing them with a previous work
Fully digital intensity modulated LIDAR
AbstractIn several applications, such as collision avoidance, it is necessary to have a system able to rapidly detect the simultaneous presence of different obstacles. In general, these applications do not require high resolution performance, but it is necessary to assure high system reliability also within critical scenarios, as in the case of partially transparent atmosphere or environment in presence of multiple objects (implying multiple echoes having different delay times.) This paper describes the algorithm, the architecture and the implementation of a digital Light Detection and Ranging (LIDAR) system based on a chirped optical carrier. This technique provides some advantages compared to the pulsed approach, primarily the reduction of the peak power of the laser. In the proposed architecture all the algorithms for signal processing are implemented using digital hardware. In this way, some specific advantages are obtained: improved detection performance (larger dynamics, range and resolution), capability of detecting multiple obstacles having different echoes amplitude, reduction of the noise effects, reduction of the costs, size and weight of the resulting equipment. The improvement provided by this fully digital solution is potentially useful in different applications such as: collision avoidance systems, 3D mapping of environments and, in general, remote sensing systems which need wide distance and dynamics
Imprecise Arithmetic for Low Power Image Processing
Sometimes reducing the precision of a numerical processor, by introducing errors, can lead to significant performance (delay, area and power dissipation) improvements without compromising the overall quality of the processing. In this work, we show how to perform the two basic operations, addition and multiplication, in an imprecise manner by simplifying the hardware implementation. With the proposed 'sloppy' operations, we obtain a reduction in delay, area and power dissipation, and the error introduced is still acceptable for applications such as image processing. © 2012 IEEE
Hardware design of LIF with Latency neuron model with memristive STDP synapses
In this paper, the hardware implementation of a neuromorphic system is
presented. This system is composed of a Leaky Integrate-and-Fire with Latency
(LIFL) neuron and a Spike-Timing Dependent Plasticity (STDP) synapse. LIFL
neuron model allows to encode more information than the common
Integrate-and-Fire models, typically considered for neuromorphic
implementations. In our system LIFL neuron is implemented using CMOS circuits
while memristor is used for the implementation of the STDP synapse. A
description of the entire circuit is provided. Finally, the capabilities of the
proposed architecture have been evaluated by simulating a motif composed of
three neurons and two synapses. The simulation results confirm the validity of
the proposed system and its suitability for the design of more complex spiking
neural network
Power Efficient Design of Parallel/Serial FIR Filters in RNS
It is well known that the Residue Number System (RNS) provides an efficient implementation of parallel FIR filters especially when the filter order and the dynamic range are high. The two main drawbacks of RNS, need of converters and coding overhead, make a serialized implementation of the FIR filter potentially disadvantageous with respect to filters implemented in the conventional number systems. In this work, we show a number of solutions which demonstrate that the power efficiency of RNS FIR filters implemented serially is maintained in ASIC technology, while in modern FPGA technology RNS implementations are less efficien
High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates
Mathematical analysis and optimization of a carrier tracking loop are presented. Due to fast changing of the carrier frequency in some satellite systems, such as Low Earth Orbit (LEO) or Global Positioning System (GPS), or some planes like Unmanned Aerial Vehicles (UAVs), high dynamic tracking loops play a very important role. In this paper an optimized tracking loop consisting of a third-order Phase Locked Loop (PLL) assisted by a second-order Frequency Locked Loop (FLL) for UAVs is proposed and discussed. Based on this structure an optimal loop has been designed. The main advantages of this approach are the reduction of the computation complexity and smaller phase error. The paper shows the simulation results, comparing them with a previous work
Energy Consumption Saving in Embedded Microprocessors Using Hardware Accelerators
This paper deals with the reduction of power consumption in embedded microprocessors. Computing power and energy efficiency are becoming the main challenges for embedded system applications. This is, in particular, the caseof wearable systems. When the power supply is provided by batteries, an important requirement for these systems is the long service life. This work investigates a method for the reduction of microprocessor energy consumption, based on the use of hardware accelerators. Their use allows to reduce the execution time and to decrease the clock frequency, so reducing the power consumption. In order to provide experimental results, authors analyze a case of study in the field of wearable devices for the processing of ECG signals. The experimental results show that the use of hardware accelerator significantly reduces the power consumption
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