Muller C-element based Decoder (MCD): A Decoder Against Transient Faults

This work extends the analysis and application of a digital error correction method called Muller C-element Decoding (MCD), which has been proposed for fault masking in logic circuits comprised of unreliable elements. The proposed technique employs cascaded Muller C-elements and XOR gates to achieve efficient error-correction in the presence of internal upsets. The error-correction analysis of MCD architecture and the investigation of C-element’s robustness are first introduced. We demonstrate that the MCD is able to produce error-correction benefit in a high error-rate of internal faults. Significantly, for a (3,6) short-length LDPC code, when the decoding process is internally error-free the MCD achieves also a gain in terms of decoding performance by comparison to the well-known Gallager Bit-Flipping method. We further consider application of MCD to a general-purpose fault-tolerant model, coded Dual Modular Redundancy (cDMR), which offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures

A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing

International audience—Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall complexity. In this paper a new hardware aware check node algorithm and its architecture is proposed. It has state-of-the-art communications performance while reducing the decoding complexity. The presented architecture has a 14 times higher area efficiency, increases the energy efficiency by factor 2.5 and reduces the latency by factor of 3.5 compared to a state-of-the-art architecture

On chip interconnects for multiprocessor turbo decoding architectures

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Les turbo-codes à roulettes

é - Le problème majeur dans l'implémentation matérielle d'un turbo-décodeur réside dans le manque de parallélisme des algorithmes de décodage MAP. Cet article propose un nouveau procédé de turbo-codage basé sur deux idées: le codage de chaque dimension par P codes convolutifs récursifs circulaires indépendants et des contraintes sur la structure de l'entrelaceur qui permet de décoder en parallèle les P codes convolutifs dans chaque dimension. La construction des codes constituants et de l'entrelaceur est décrite et analysée. Un haut degré de parallélisme est obtenu avec des performances équivalentes ou meilleures que les meilleurs turbo-codes connus. L'architecture parallèle du décodeur permet de réduire la complexité du turbo-décodeur pour des applications à très hauts débits

The Physicist's Guide to the Orchestra

An experimental study of strings, woodwinds (organ pipe, flute, clarinet, saxophone and recorder), and the voice was undertaken to illustrate the basic principles of sound production in music instruments. The setup used is simple and consists of common laboratory equipment. Although the canonical examples (standing wave on a string, in an open and closed pipe) are easily reproduced, they fail to explain the majority of the measurements. The reasons for these deviations are outlined and discussed.Comment: 11 pages, 10 figures (jpg files). Submitted to European Journal of Physic

Improving Network-on-Chip-based Turbo Decoder Architectures

In this work novel results concerning Networkon- Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support doublebinary codes, by exploiting bit-level and pseudo-floatingpoint representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 d

Low complexity soft demapping for non-binary LDPC codes

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Identification of honeycomb sandwich properties by high-resolution modal analysis

A method is proposed to identify the mechanical properties of the skin and core materials of honeycomb sandwich. All the elastic coefficients and loss-factors that matter in the dynamics of a panel in the thick-plate approximation are identified. To this end, experimental natural modes (i.e. eigenmodes of the damped system) are compared to the numerical modes of a large sandwich panel (lx,y/h ≃ 80). The chosen generic model for the visco-elastic behaviour of the materials is E (1 + jη). The numerical modes are computed by means of a Rayleigh-Ritz procedure and their dampings are predicted according to the visco-elastic model. The frequencies and dampings of the natural modes of the panel are estimated experimentally by means of a high-resolution modal analysis technique. An optimisation procedure yields the desired coefficients. A sensitivity analysis assess the reliability of the method

Application of modal analysis and synthesis of reed and pipe to numerical simulations of a clarinet

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Étude modale d'une clarinette

No abstract provide