Scheduling of Behavioral VHDL by Retiming Techniques

Abstract In this paper we present a new approach to the scheduling of behavioral VHDL descriptions for control-ow dominated applications containing a large number of nested conditionals and data dependent loops. The proposed algorithm is able to schedule and re-schedule descriptions for optimization subject to various cost functions. The timing of the I/O signals can be c ompletely xed, partially xed o r left to the scheduler. In this case the algorithm produces a schedule such that the number of clock cycles required f o r a c omplete execution of the behavioral description is minimized. Scheduling is performed a s a b ehavioral VHDL code transformation and allows taking advantage of all the power of commercial RT synthesis systems. The corresponding problem is solved b ased on an analogy to the retiming problem on RT-level networks which can be solved i n p olynomial time. The eciency of our approach is demonstrated on various examples