Safety Verification of Phaser Programs

We address the problem of statically checking control state reachability (as in possibility of assertion violations, race conditions or runtime errors) and plain reachability (as in deadlock-freedom) of phaser programs. Phasers are a modern non-trivial synchronization construct that supports dynamic parallelism with runtime registration and deregistration of spawned tasks. They allow for collective and point-to-point synchronizations. For instance, phasers can enforce barriers or producer-consumer synchronization schemes among all or subsets of the running tasks. Implementations %of these recent and dynamic synchronization are found in modern languages such as X10 or Habanero Java. Phasers essentially associate phases to individual tasks and use their runtime values to restrict possible concurrent executions. Unbounded phases may result in infinite transition systems even in the case of programs only creating finite numbers of tasks and phasers. We introduce an exact gap-order based procedure that always terminates when checking control reachability for programs generating bounded numbers of coexisting tasks and phasers. We also show verifying plain reachability is undecidable even for programs generating few tasks and phasers. We then explain how to turn our procedure into a sound analysis for checking plain reachability (including deadlock freedom). We report on preliminary experiments with our open source tool

Low-energy standby-sparing for hard real-time systems

Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardwareredundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for lowenergy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique to use standby sparing for hard real-time systems with limited energy budgets. The principal contribution of this work is an online energymanagement technique which is specifically developed for standby-sparing systems that are used in hard real-time applications. This technique operates at runtime and exploits dynamic slacks to reduce the energy consumption while guaranteeing hard deadlines. We compared the low-energy standby-sparing (LESS) system with a low-energy timeredundancy system (from a previous work). The results show that for relaxed time constraints, the LESS system is more reliable and provides about 26% energy saving as compared to the time-redundancy system. For tight deadlines when the timeredundancy system is not sufficiently reliable (for safety-critical application), the LESS system preserves its reliability but with about 49% more energy consumptio

Predictable Implementation of Real-Time Applications on Multiprocessor Systems on Chip

Worst-case execution time (WCET) analysis and, in general, the predictability of real-time applications implemented on multiprocessor systems has been addressed only in very restrictive and particular contexts. One important aspect that makes the analysis difficult is the estimation of the system\u27s communication behavior. The traffic on the bus does not solely originate from data transfers due to data dependencies between tasks, but is also affected by memory transfers as result of cache misses. As opposed to the analysis performed for a single processor system, where the cache miss penalty is constant, in a multiprocessor system each cache miss has a variable penalty, depending on the bus contention. This affects the tasks\u27 WCET which, however, is needed in order to perform system scheduling. At the same time, the WCET depends on the system schedule due to the bus interference. In this context, we present an approach to worst-case execution time analysis and system scheduling for real-time applications implemented on multiprocessor SoC architectures. We will also address the bus scheduling policy and its optimization, which are of huge importance for the performance of such predictable multiprocessor applications

Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction

Recent research has shown that combining dynamic voltage scaling (DVS) and adaptive body bias (ABB) techniques achieve the highest reduction in embedded systems energy dissipation [1]. In this paper we show that it is possible to produce comparable energy saving to that obtained using combined DVS and ABB techniques but with reduced hardware cost achieved by employing processing elements (PEs) with separate DVS or ABB capability. A co-synthesis methodology which is aware of tasks’ power-composition profile (the ratio of the dynamic power to the leakage power) is presented. The methodology selects voltage scaling capabilities (DVS, ABB, or combined DVS and ABB) for the PEs, maps, schedules, and voltage scales applications given as task graphs with timing constraints, aiming to dynamic and leakage energy reduction at low hardware cost. We conduct detailed experiments, including a real-life example, to demonstrate the effectiveness of our methodology. We demonstrate that it is possible to produce designs that contain PEs with only DVS or ABB technique but have energy dissipation that are only 4.4% higher when compared with the same designs that employ PEs with combined DVS and ABB capabilities

In Vivo Imaging to Characterize Dynamic Tissue Responses after Neural Electrode Implantation

Implantable neural electrodes are promising technologies to restore motor, sensory, and cognitive function in many neural pathologies through brain-computer interfacing (BCI). Many BCI applications require electrode implantation within neural tissue to resolve and/or modulate the physiological activity of individual neurons via electrical recording and stimulation. This invasive implantation leads to acute and long-term deterioration of both the electrode device as well as the neurons surrounding the device. Ultimately, damage to the electrode and neural tissue results in electrode recording failure within the first years after implantation. Many strategies to improve BCI longevity focus on mitigating tissue damage through improving neuronal survival or reducing inflammatory activity around implants. Despite incremental improvements, electrode failure persists as an obstacle to wide-spread clinical deployment of BCIs. This can be partly attributed to an incomplete understanding of the biological correlates of recording performance. These correlates have largely been identified through post-mortem histological staining, which cannot capture dynamic changes in cellular physiology and morphology. In the following dissertation, we use longitudinal two-photon in vivo imaging to quantify how neurons, microglia, and meningeal immune cells are affected by an intracortical electrode during and after implantation in mouse cortex. We go beyond conventional histological techniques to show the time-course of neuronal injury and microglial recruitment after implantation. Neuronal injury occurs instantaneously, with prolonged, high calcium levels evident in neurons within 100 µm of implants. Microglial activation occurs within minutes of implantation and subsequent microglial encapsulation of electrodes can be modulated by bioactive surface coatings. Within the first day post-implant, there is high trafficking of peripheral immune cells through venules at the surface of the brain as well as along the electrode’s shank at the surface of the brain. Over the next month, calcium activity in neurons increases while the collagenous meningeal tissues at the surface of the brain thicken. We further show that meningeal thickening can have profound implications for devices implanted into non-human primates as well. In sum, these results define new potential therapeutic targets and windows that could improve the longevity of implantable neural electrodes

The Operation of the Trade Agreements Program in Overcoming Barriers to Hemisphere Trade

With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy or/and performance optimization will be sufficiently accurate and efficient. In this paper we propose an on-line temperature aware dynamic voltage and frequency scaling (DVFS) technique which is able to exploit both static and dynamic slack. The approach implies an offline temperature aware optimization step and on-line voltage/frequency settings based on temperature sensor readings. Most importantly, the presented approach is aware of the frequency/temperature dependency, by which important additional energy savings are obtained

Pengaruh store atmosphere dan price discount terhadap keputusan pembelian impulse buying pelanggan Carrefour Market

Penelitian bertujuan untuk mengetahui pengaruh store atmosphere dan price discount terhadap keputusan pembelian impulse buying pelanggan Carrefour Market. Sampel penelitian sebanyak 100 orang pelanggan Carrefour Malang, yang diambil secara acak, teknik pengumpulan menggunakan kuesioner, adapun teknik analisis Regresi Linear Berganda. Hasil penelitian menunjukkan bahwa store atmosphere berpengaruh positif dan signifikan terhadap keputusan pembelian impulse buying, price discount berpengaruh positif dan signifikan terhadap keputusan pembelian impulse buying. Hasil penelitian ini menunjukkan bahwa perilaku impulse buying tercipta karena strategi Carrefour dalam menciptakan store atmosphere yang menarik dan kebijakan price discount pada beberapa produk yang dijual

Schedulability-Driven Frame Packing for Multi-Cluster Distributed Embedded Systems

We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable. Thus, we have also proposed a schedulability analysis for applications consisting of mixed event-triggered and time-triggered processes and messages, and a worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach

Flexibility Driven Scheduling and Mapping for Distributed Real-Time Systems

In this paper we present an approach to mapping and scheduling of distributed hard real-time systems, aiming at improving the flexibility of the design process. We consider an incremental design process that starts from an already existing system running a set of applications, with preemptive priority based scheduling at the process level, and time triggered static scheduling at the communication level. We are interested to implement new functionality so that the already running applications are disturbed as little as possible and there is a good chance that, later, new functionality can easily be added to the resulted system. The mapping and scheduling problems are considered in the context of a realistic communication model based on a TDMA protocol. Extensive experiments as well as a real life example demonstrate the relevance of this problem and the efficiency of our solutions. 1