Channel-Hot-Carrier degradation of strained MOSFETs : A device level and nanoscale combined approach

Strained MOSFETs with SiGe at the source/drain regions and different channel lengths have been studied at the nanoscale with a conductive atomic force microscope (CAFM) and at device level, before and after channel-hot-carrier (CHC) stress. The results show that although strained devices have a larger mobility, they are more sensitive to CHC stress. This effect has been observed to be larger in short channel devices. The higher susceptibility of strained MOSFETs to the stress has been related to a larger density of defects close to the diffusions, as suggested by CAFM data

Gate current analysis of AlGaN/GaN on silicon heterojunction transistors at the nanoscale

The gate leakage current of AlGaN/GaN (on silicon)high electron mobility transistor(HEMT) is investigated at the micro and nanoscale. The gate current dependence (25-310 °C) on the temperature is used to identify the potential conduction mechanisms, as trap assisted tunneling or field emission. The conductive atomic force microscopy investigation of the HEMT surface has revealed some correlation between the topography and the leakage current, which is analyzed in detail. The effect of introducing a thin dielectric in the gate is also discussed in the micro and the nanoscale

Variability and reliability at the nanoscale of gate dielectrics of MOS devices and graphene based structures

En el primer capítulo de ésta tesis, se les dará un resumen del transistor MOSFET y de las consecuencias del escalado de dispositivos electrónicos. También se explican las alternativas posibles para permitir mantener dicha tendencia, como la introducción de dieléctricos high-k y el potencial del grafeno para aplicaciones en nanoelectrónica. El segundo capítulo se dedica a describir con más detalle el AFM (Atomic Force Microscope), que se ha utilizado para investigar las propiedades eléctricas de los diferentes materiales en la nanoescala. En el tercer capítulo, diferentes condiciones de fabricación de dispositivos basados en capas de HfO2, tales como la temperatura de recocido (y polycrystallization), el espesor y el precursor con el que se crece dichas capas, serán investigadas en la nanoescala. La influencia de una tensión eléctrica a nivel del dispositivo también se estudió. En el capítulo 4, el impacto de las diferentes estreses eléctricos en las propiedades eléctricas de los MOSFETs basados en capas de SiON ultrafinas se investigó a escala manométrica. El uso de un CAFM, el óxido de puerta ha sido analizada después de una NBTI (Bias Temperature Instability) y CHC estrés (Canal portadores calientes). Puesto que con la punta CAFM áreas muy pequeñas pueden ser estudiados, se analizó la degradación inducida a diferentes regiones del óxido de puerta a lo largo del canal. Capítulo 5 describe la invención de un enfoque completamente nuevo para mejorar significativamente las propiedades mecánicas y eléctricas intrínsecas de puntas CAFM disponibles en el mercado por recubrimiento de las mismas con grafeno. Por último, en el capítulo 6, el uso de grafeno para aplicaciones en nanoelectrónica será investigado en la nanoescala. Un aspecto que se analizará es la presencia de ondulaciones, las arrugas y los límites de grano, que se muestran para aumentar la variabilidad de dispositivo a dispositivo. También se estudió el impacto del sustrato sobre el que se transfiere a grafeno. Dado que el grafeno se ha empezado a ser utilizado como electrodo superior en los dispositivos de memoria, en la segunda parte de este capítulo, la variabilidad y la fiabilidad de grafeno-aislante-semiconductor estructuras (GIS) basado en HfO2 serán previamente investigados.In the first chapter of this thesis, the MOSFET transistor and an overview of the implications of ongoing device shrinking will be given. Possible alternatives to allow the scaling down such as the introduction of high-k dielectrics and the potential of graphene for nanoelectronic applications are also explained. The second chapter will be devoted to describe in more detail the AFM (Atomic Force Microscope), which has been used to investigate the electrical properties of different materials at the nanoscale. In the third chapter, different fabrication conditions of HfO2 layers based devices, such as the annealing temperature (and polycrystallization), the thickness and the precursor with which it was grown will be investigated at the nanoscale. The influence of an electrical stress at the device level is also studied. In chapter 4, the impact of different electrical stresses on the nanoscale electrical properties of ultra-thin SiON based MOSFETs is investigated. Using a CAFM, the gate oxide has been analyzed after a BTI (Bias Temperature Instability) and CHC (Channel Hot Carriers) stress. Since with the CAFM tip very small areas can be studied, the degradation induced at different regions of the gate oxide along the channel was analyzed. Chapter 5 describes the invention of a completely new approach to significantly improve the intrinsic mechanical and electrical properties of commercially available CAFM tips by coating them with graphene. Finally, in chapter 6, the usability of graphene for nanoelectronic applications will be investigated at the nanoscale. One aspect that will be analyzed is the presence of corrugations, wrinkles and grain boundaries, which are shown to increase the device-to-device variability. The impact of the substrate on which graphene is transferred to will be also studied. Since graphene has been recently started to be used as top electrode in memory devices, in the second part of this chapter, the variability and reliability of Graphene-Insulating-Semiconductor (GIS) structures based on HfO2 will be preliminarily investigated

Variability and reliability at the nanoscale of gate dielectrics of MOS devices and graphene based structures

In the first chapter of this thesis, the MOSFET transistor and an overview of the implications of ongoing device shrinking will be given. Possible alternatives to allow the scaling down such as the introduction of high-k dielectrics and the potential of graphene for nanoelectronic applications are also explained. The second chapter will be devoted to describe in more detail the AFM (Atomic Force Microscope), which has been used to investigate the electrical properties of different materials at the nanoscale. In the third chapter, different fabrication conditions of HfO2 layers based devices, such as the annealing temperature (and polycrystallization), the thickness and the precursor with which it was grown will be investigated at the nanoscale. The influence of an electrical stress at the device level is also studied. In chapter 4, the impact of different electrical stresses on the nanoscale electrical properties of ultra-thin SiON based MOSFETs is investigated. Using a CAFM, the gate oxide has been analyzed after a BTI (Bias Temperature Instability) and CHC (Channel Hot Carriers) stress. Since with the CAFM tip very small areas can be studied, the degradation induced at different regions of the gate oxide along the channel was analyzed. Chapter 5 describes the invention of a completely new approach to significantly improve the intrinsic mechanical and electrical properties of commercially available CAFM tips by coating them with graphene. Finally, in chapter 6, the usability of graphene for nanoelectronic applications will be investigated at the nanoscale. One aspect that will be analyzed is the presence of corrugations, wrinkles and grain boundaries, which are shown to increase the device-to-device variability. The impact of the substrate on which graphene is transferred to will be also studied. Since graphene has been recently started to be used as top electrode in memory devices, in the second part of this chapter, the variability and reliability of Graphene-Insulating-Semiconductor (GIS) structures based on HfO2 will be preliminarily investigated.En el primer capítulo de ésta tesis, se les dará un resumen del transistor MOSFET y de las consecuencias del escalado de dispositivos electrónicos. También se explican las alternativas posibles para permitir mantener dicha tendencia, como la introducción de dieléctricos high-k y el potencial del grafeno para aplicaciones en nanoelectrónica. El segundo capítulo se dedica a describir con más detalle el AFM (Atomic Force Microscope), que se ha utilizado para investigar las propiedades eléctricas de los diferentes materiales en la nanoescala. En el tercer capítulo, diferentes condiciones de fabricación de dispositivos basados en capas de HfO2, tales como la temperatura de recocido (y polycrystallization), el espesor y el precursor con el que se crece dichas capas, serán investigadas en la nanoescala. La influencia de una tensión eléctrica a nivel del dispositivo también se estudió. En el capítulo 4, el impacto de las diferentes estreses eléctricos en las propiedades eléctricas de los MOSFETs basados en capas de SiON ultrafinas se investigó a escala manométrica. El uso de un CAFM, el óxido de puerta ha sido analizada después de una NBTI (Bias Temperature Instability) y CHC estrés (Canal portadores calientes). Puesto que con la punta CAFM áreas muy pequeñas pueden ser estudiados, se analizó la degradación inducida a diferentes regiones del óxido de puerta a lo largo del canal. Capítulo 5 describe la invención de un enfoque completamente nuevo para mejorar significativamente las propiedades mecánicas y eléctricas intrínsecas de puntas CAFM disponibles en el mercado por recubrimiento de las mismas con grafeno. Por último, en el capítulo 6, el uso de grafeno para aplicaciones en nanoelectrónica será investigado en la nanoescala. Un aspecto que se analizará es la presencia de ondulaciones, las arrugas y los límites de grano, que se muestran para aumentar la variabilidad de dispositivo a dispositivo. También se estudió el impacto del sustrato sobre el que se transfiere a grafeno. Dado que el grafeno se ha empezado a ser utilizado como electrodo superior en los dispositivos de memoria, en la segunda parte de este capítulo, la variabilidad y la fiabilidad de grafeno-aislante-semiconductor estructuras (GIS) basado en HfO2 serán previamente investigados

Channel-Hot-Carrier degradation of strained MOSFETs : A device level and nanoscale combined approach

Strained MOSFETs with SiGe at the source/drain regions and different channel lengths have been studied at the nanoscale with a conductive atomic force microscope (CAFM) and at device level, before and after channel-hot-carrier (CHC) stress. The results show that although strained devices have a larger mobility, they are more sensitive to CHC stress. This effect has been observed to be larger in short channel devices. The higher susceptibility of strained MOSFETs to the stress has been related to a larger density of defects close to the diffusions, as suggested by CAFM data

Degradation of polycrystalline HfO2-based gate dielectrics under nanoscale electrical stress

The evolution of the electrical properties of HfO2/SiO2/Si dielectric stacks under electrical stress has been investigated using atomic force microscope-based techniques. The current through the grain boundaries (GBs), which is found to be higher than thorough the grains, is correlated to a higher density of positively charged defects at the GBs. Electrical stress produces different degradation kinetics in the grains and GBs, with a much shorter time to breakdown in the latter, indicating that GBs facilitate dielectric breakdown in high-k gate stacks

Gate current analysis of AlGaN/GaN on silicon heterojunction transistors at the nanoscale

The gate leakage current of AlGaN/GaN (on silicon)high electron mobility transistor(HEMT) is investigated at the micro and nanoscale. The gate current dependence (25-310 °C) on the temperature is used to identify the potential conduction mechanisms, as trap assisted tunneling or field emission. The conductive atomic force microscopy investigation of the HEMT surface has revealed some correlation between the topography and the leakage current, which is analyzed in detail. The effect of introducing a thin dielectric in the gate is also discussed in the micro and the nanoscale