Design of a low-voltage op-amp-less ASDM to linearise VCO-ADC

A very simple asynchronous sigma delta modulator design for linearisation of VCO ADC's is presented. The circuit only consists of a passive feedback filter and a Schmitt Trigger. By proper sizing, the non-linearity error can be reduced to well below 0.12% for input signals that go almost rail-to-rail. The design has been manufactured in the low power version of TSMC 65 nm technology and was measured at a 1 V power supply

Continuous time delta sigma modulation with PWM pre-coding and binary g(m) blocks

A very simple technique to implement the first integrator of a continuous-time delta sigma modulator (CT-DSM) is presented. In the approach, the CT-DSM is preceded by a pulse-width modulator to convert the input signal to a pseudo-digital continuous time waveform. As a result, the first integrator of the DSM can be implemented with a capacitor and a switched current source, with inherent linearity. To illustrate the concept, it has been applied to the design of a second-order CT-DSM in 65 nm CMOS technology

Analytical expressions for the distortion of asynchronous sigma-delta modulators

This brief investigates the commonly used asynchronous sigma-delta modulator, which consists of a Schmitt trigger and a continuous-time loop filter. A detailed analysis is presented to accurately predict the distortion of such modulators. The extracted expressions are compared with simulation results, and they illustrate an excellent match. The results are also compared with a previous work by Roza, and they show a drastic improvement in accuracy

Highly linear VCO for use in VCO-ADCs

A very simple ring-oscillator voltage-controlled oscillator (VCO) structure for use in VCO-ADC applications is presented. It has a greatly improved linearity compared with previously published VCOs. Measurement results of a 1 V, 65 nm CMOS prototype confirm the effectiveness of the proposed approach

Analyzing distortion in ASDMs with loop delay

Recently nearly exact expressions for the distortion in a commonly used family of Pulse Width Modulators (PWMs) known as Asynchronous Sigma Delta Modulators (ASDMs) were presented. Such an ASDM consists of a feedback loop with a schmitt-trigger (or a comparator), and a continuous time loop filter. However these previous results are not yet practically applicable because the effect of unavoidable loop delay (e.g. in the schmitt trigger) was not taken into account. Therefore we now present a more general theory that is also valid when there is a nonzero loop delay. A comparison of the resulting equations with computer simulations demonstrated a very good matching, confirming the validness of the theory. This way, a designer can now easily understand the relationship between the loop filter dynamics and the linearity of an ASDM

Improved offline calibration for DAC mismatch in low OSR Sigma Delta ADCs with distributed feedback

We present an offline calibration method to correct the non-linearity due to DAC element mismatch in distributed feedback SigmaDelta-modulation A/D-converters. The improvement over previous methods is that not only the first feedback DAC is calibrated, but also the DACs that are coupled to later stages can be calibrated as well. This is needed in the case of Sigma Delta modulators with a low OSR, where the contribution of the second feedback DAC should not be neglected. The technique is based on a calibration measurement with a two-tone input signal

A mostly digital VCO-based CT-SDM with third-order noise shaping

This paper presents the architectural concept and implementation of a mostly digital voltage-controlled oscillator-analog- to-digital converter (VCO-ADC) with third-order quantization noise shaping. The system is based on the combination of a VCO and a digital counter. It is shown how this combination can function as a continuous-time integrator to form a high-order continuous-time sigma-delta modulator (CT-SDM). The counter consists only of digital building blocks, and the VCOs are implemented using ring oscillators, which are also digital-friendly. No traditional analog blocks, such as opamps, OTAs, or comparators, are used. As a proof of concept, we have implemented a third-order VCO-based CT-SDM for a 10-MHz bandwidth in the low-power version of a 65-nm CMOS technology. This prototype shows a measured performance of 71/66.2/62.5-dB DR/SNR/SNDR at a 10-MHz bandwidth while consuming 1.8 mW from a 1.0-V analog and 1.9 mW from a 1.2-V digital supply. With digital calibration, the nonlinearity could be pushed below the noise level, leading to an improved peak SNDR of 66 dB

Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping

Recently an architecture for a nearly digital VCO ADC with high order quantization noise shaping was presented. Unfortunately, the structure is affected by the non-linearity of the first VCO. In this manuscript, we report experimental results of a potential solution for this problem: placing a pulse width modulator (PWM) in front of this first VCO. The work is based on a prototype VCO-ADC with 3rd order noise shaping and 10 MHz bandwidth, implemented in a 65 nm CMOS technology. For small input signals the circuit behaves as expected. Unfortunately for larger input signal levels the noise of the prototype is significantly higher than was expected from the a priori simulations. Upon investigation, this is attributed to subtle (mismatch induced) intermodulation effects. Overall the prototype's measured performance leads to a DR/SNR/SNDR of 67.4/59/55.4 dB at a 10MHz bandwidth while consuming 2.3mW from a 1.0V analog and 2mW from a 1.2V digital supply