278 research outputs found
Mouse models of osteoarthritis and joint injury
Thesis (S.B.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 39-40).Nearly 21 million Americans are affected by osteoarthritis, a complex disease characterized by degenerative lesions to the articular cartilage and subchondral bone in the joints. The complexity of the disease makes the use of human models impractical and complicated. Therefore, various animal models have been developed to study the progression of OA and possible therapeutic techniques. Of those models, mouse models play an integral part because of their cost-effectiveness, favorable logistics, and ability to be genetically manipulated. Three main mouse models were reviewed: (1) genetic deletion, (2) treadmill running, and (3) surgically induced injuries. Several strains of knockout mice have been develop in the past 10 years and they provide a great opportunity to study the evolution of OA. Up until now, treatment for OA has been pain management-related, but the development of more advanced mouse models has laid out the framework for possible OA preventing and repairing techniques.by Jose Enrique Avedillo.S.B
Holding Dissapearance in RTD-based Quantizers
Multiple-valued Logic (MVL) circuits are one of the most attractive
applications of the Monostable-to-Multistable transition Logic (MML), and they
are on the basis of advanced circuits for communications. The operation of such
quantizer has two steps : sampling and holding. Once the quantizer samples the
signal, it must maintain the sampled value even if the input changes. However,
holding property is not inherent to MML circuit topologies. This paper analyses
the case of an MML ternary inverter used as a quantizer, and determines the
relations that circuit representative parameters must verify to avoid this
malfunction.Comment: Submitted on behalf of TIMA Editions
(http://irevues.inist.fr/tima-editions
Using Multi-Threshold Threshold Gates in RTD-based Logic Design. A Case Study
The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits
are Threshold Gates (TGs) instead of the conventional Boolean gates (AND, OR,
NAND, NOR) due to the fact that, when designing with RTDs, threshold gates can
be implemented as efficiently as conventional ones, but realize more complex
functions. Recently, RTD structures implementing Multi-Threshold Threshold
Gates (MTTGs) have been proposed which further increase the functionality of
the original TGs while maintaining their operating principle and allowing also
the implementation of nanopipelining at the gate level. This paper describes
the design of n-bit adders using these MTTGs. A comparison with a design based
on TGs is carried out showing advantages in terms of latency, device counts and
power consumption.Comment: Submitted on behalf of TIMA Editions
(http://irevues.inist.fr/tima-editions
Protegerse del proteccionismo
En las últimas semanas se han vuelto a oÃr voces en favor del proteccionismo como respuesta a la severa caÃda de la demanda mundial y la dificultad de aplicar polÃticas fiscales expansivas en una economÃa abierta.
Tras el Crack de 1929, EEUU aplicó una dura polÃtica proteccionista como medio para preservar el empleo y la actividad económica nacional. Ello se demostró como uno de los grandes errores de polÃtica económica, que profundizaron y alargaron la recesión. A pesar de las lecciones del pasado, en las últimas semanas se han vuelto a oÃr voces en favor del proteccionismo como respuesta a la severa caÃda de la demanda mundial y la dificultad de aplicar polÃticas fiscales expansivas en una economÃa abierta. La coordinación de los paÃses y el refuerzo de las instituciones internacionales son esenciales para hacer frente a este movimiento
Two-phase RTD-CMOS pipelined circuits
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) allowing high through output. Resonant tunneling diode (RTD)-based MOBILE nanopipelined circuits have been reported using different clock schemes including a four-phase strategy and a single-phase clock scheme. In particular, significant power advantages of single-phase RTD-CMOS MOBILE circuits over pure CMOS have been shown. This letter compares the RTD-CMOS realizations using a single clock and a novel two-phase clock solution. Significant superior robustness and performance in terms of power and area are obtained for the two-phase implementations
RTD based logic circuits using generalized threshold gates
Many logic circuit applications of Resonant Tunneling
Diodes are based on the MOnostable-BIstable Logic Element
(MOBILE). Threshold logic is a computational model
widely used in the design of MOBILE circuits, i.e. these circuits
are built from threshold gates (TGs). The MOBILE realization
of generalized threshold gates is being investigated.
Multi-Threshold Threshold Gates (MTTGs) have been proposed
which further increase the functionality of the original TGs.
Recently, we have proposed a novel MOBILE circuit topology
obtained by fundamental properties of threshold functions. This
paper describes the design of n-bit adders using these novel
MOBILE circuit topologies. A comparison with designs based
on TGs and MTTGs is carried out showing advantages in
terms of speed and power delay product and device counts.España, Gobierno TEC2007-67245Junta de AndalucÃa EXC/2007/TIC-296
Efficient realization of a threshold voter for self-purging redundancy
The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, the threshold voter. A very efficient implementation of this voter is presented which uses a decomposition technique to substantially reduce the circuit complexity and delay, as compared to alternative implementations.Comisión Interministerial de Ciencia y TecnologÃa TIC97-064
Efficient state reduction methods for PLA-based sequential circuits
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms described in detail. Results on machines from the literature and from the MCNC benchmark set are shown. The area of the PLA implementation of the combinational component and the design time are used as figures of merit. The comparison of such parameters, when the state reduction step is included in the design process and when it is not, suggests that fast state-reduction heuristics should be implemented within FSM automatic synthesis systems
Sorting networks implemented as νMOS circuits
A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.Comisión Interministerial de Ciencia y TecnologÃa TIC95-0094, TIC97-064
Steep-slope Devices for Power Efficient Adiabatic Logic Circuits
Reducing supply voltage is an effective way to reduce power consumption, however, it greatly reduces CMOS circuits speed. This translates in limitations on how low the supply voltage can be reduced in many applications due to frequency constraints. In particular, in the context of low voltage adiabatic circuits, another well-known technique to save power, it is not possible to obtain satisfactory power-speed trade-offs. Tunnel field-effect transistors (TFETs) have been shown to outperforms CMOS at low supply voltage in static logic implementations, operation due to their steep subthreshold slope (SS), and have potential for combining low voltage and adiabatic. To the best of our knowledge, the adiabatic circuit topologies reported with TFETs do not take into account the problems associated with their inverse current due to their intrinsic p-i-n diode. In this paper, we propose a solution to this problem, demonstrating that the proposed modification allows to significantly improving the performance in terms of power/energy savings compared to the original ones, especially at medium and low frequencies. In addition, we have evaluated the relative advantages of the proposed TFET adiabatic circuits, both at gate and architecture levels, with respect to their static implementations, demonstrating that these are greater than for FinFET transistor designs.
Index Terms—Adiabatic logic, TunnelPeer reviewe
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