Many logic circuit applications of Resonant Tunneling
Diodes are based on the MOnostable-BIstable Logic Element
(MOBILE). Threshold logic is a computational model
widely used in the design of MOBILE circuits, i.e. these circuits
are built from threshold gates (TGs). The MOBILE realization
of generalized threshold gates is being investigated.
Multi-Threshold Threshold Gates (MTTGs) have been proposed
which further increase the functionality of the original TGs.
Recently, we have proposed a novel MOBILE circuit topology
obtained by fundamental properties of threshold functions. This
paper describes the design of n-bit adders using these novel
MOBILE circuit topologies. A comparison with designs based
on TGs and MTTGs is carried out showing advantages in
terms of speed and power delay product and device counts.España, Gobierno TEC2007-67245Junta de Andalucía EXC/2007/TIC-296

Avedillo de Juan, María José

Pettenghi Roldán, Héctor

Quintana Toledo, José María

English

idUS. Depósito de Investigación Universidad de Sevilla

1Abstract - Many logic circuit applications of Resonant Tun-neling Diodes are based on the MOnostable-BIstable Logic Ele-ment (MOBILE). Threshold logic is a computational modelwidely used in the design of MOBILE circuits, i.e. these cir-cuits are built from threshold gates (TGs). The MOBILE real-ization of generalized threshold gates is being investigated.Multi-Threshold Threshold Gates (MTTGs) have been proposedwhich further increase the functionality of the original TGs.Recently, we have proposed a novel MOBILE circuit topologyobtained by fundamental properties of threshold functions. Thispaper describes the design of n-bit adders using these novelMOBILE circuit topologies. A comparison with designs basedon TGs and MTTGs is carried out showing advantages interms of speed and power delay product and device counts.IndexTerms - Resonant Tunneling Diodes, MOBILE, Thresholdgate, nanopipelining.I. INTRODUCTIONResonant tunnelling diodes (RTDs) are very fast nonlinear circuit elements which exhibit a negative differen-tial resistance (NDR) region in their current-voltage char-acteristics (Figure 1a) which can be exploited tosignificantly increase the functionality implemented by asingle gate. Circuit applications of RTDs are mainly based onthe MOnostable-BIstable Logic Element (MOBILE) [1]. TheMOBILE (Figure 1a) is a rising edge triggered current con-trolled gate which consists of two RTDs connected in seriesand driven by a switching bias voltage . Whenis low, both RTDs are in the on-state (or low resistance state)and the circuit is monostable. Increasing to an appro-priate maximum value ensures that only the device with thelowest peak current switches (quenches) from the on-state tothe off-state (the high resistance state). Output is high if thedriver RTD is the one which switches and it is low if the loadswitches. Assuming equal current densities for both RTDs,peak currents are proportional to RTD areas, and , forload and driver respectively. Thus, the load switches(the output goes to low or “0”) and if otherwisethe driver switches (the output goes to high or“1”). Logic functionality can be achieved if the peak current ofone of the RTDs is controlled by an input. In the configurationfor an inverter MOBILE shown in Figure 1b, the peak currentof the driver RTD can be modulated using the external inputsignal . During a critical period when rises, thevoltage at the output node goes to one of the two stablestates (low or high), corresponding to “0” and “1” in binarylogic. RTD areas are selected such that the value of the outputdepends on whether the external input signal is “1” or“0”. For , the output node maintains its value evenif the input changes. That is, this circuit structure is self-latch-ing allowing to implement pipeline at the gate level withoutany area overhead associated to the addition of the latcheswhich allows very high throughoutput.The operating principle of MOBILE is extremely well suitedto implement the arithmetic operation on which Threshold Gates[2] (TGs) are based. The circuit topology in Figure 1b has beenextended to systematically implement TGs [3][4] and have beenexperimentally demonstrated [4][5]. TGs are a generalization ofconventional Boolean gates, able to implement also more com-plex functions which is atractive from the point of logic design:1.This effort was partially supported by the Spanish Governmentunder project TEC2007-67245 and Andalusian Goverment throughproject EXC/2007/TIC-2961.V bias( ) V biasV biasλ1 λ2λ1 λ2<V outλ2 λ1< V outV in V biasV outV inV bias 1=LoadDriverV biasV out(a)-1 -0.5 0.5 1-2-112VRTD (V)IRTD (mA)peakcurrentcurrentvalleypeakvoltageV inV outNDR1NDR2V bias(b)Figure 1.-a) Basic MOBILE, (b) MOBILE inverter.λ2λ1λ3λ2λ1λ1 λ2<λ2 λ1 λ3+<RTD based Logic Circuits Using Generalized Threshold Gates1Héctor Pettenghi, María J. Avedillo, and José M. QuintanaInstituto de Microelectrónica de Sevilla-Centro Nacional de Microelectrónica-Consejo Superior de Investigaciones Cientificas (IMSE-CNM-CSIC), Universidad de Sevilla (US)E-mail: {hector, avedillo, josem}@imse.cnm.esless gates and interconections. More recently, generalizedthreshold gates, also suitable to be realized with MOBILERTD structures, are being investigated [6], [7], [8], [9]In this paper we design, evaluate and compare 8-bit nano-pipelined adders implemented with different threshold-basedMOBILE logic styles. The rest of the paper is organized asfollows. Section II describes and compares several thresholdgate based MOBILE styles. Architectures of 8-bit addersusing these gates are described, simulated and compared inSection III. In the conclusions the results obtained are dis-cussed.II. GENERALIZED THRESHOLD GATE MOBILEFor the sake of clarity, let us consider a two-input function,the EXOR, , to illustrate the relation-ship between generalized threshold logic and MOBILE circuittopologies, as well as to introduce the different topologies.This function is not a threshold function however, a number ofMOBILE implementations are possible, if we generalize thethreshold logic concepts.A TG [2] is defined as a logic gate with n binary input var-iables, , one binary output , and for whichthere is a set of real numbers: threshold T, andweights , such that its input-output relation-ship is defined as iff , and oth-erwise.Non threshold functions require a network of TGs to beimplemented. Figure 2 depicts the TG networks realizing thetwo-input EXOR (Figure 2a). Bias signals to operate cas-caded MOBILE-type circuits [4] are also shown (Figure 2b).A four phase (evaluation, hold, reset and wait) overlappingclocking scheme is used. Second stage evaluates (rising edgeof Vbias2) while the first stage is in the hold phase (Vbias1high). For a number of logic levels greater than three, fourbias signals are required. In one clock period all the gates areactivated. Data can be processed at a frequency determinedby the operation speed of four chained MOBILE gates.Figure 3 depicts its realization as a Multi-Threshold Thresh-old Gate (MTTG) [6]. MTTGs are a generalization of the con-ventional TGs in which there are K thresholds, T1,...TK, ratherthan the usual single threshold, T. K + 1 serie connected RTDsare required instead of the two of the basic MOBILE. The out-put of a two-input two-threshold MTTG is 1 forand 0 for and. Clearly, for w1 = w2 = 1, T1 = 1, and T2= 2, this corresponds to the two-input EXOR function.Figure 4 depicts a realization reported in [7] and which canbe explained as a TG over an extended input set (GTG1). Thetwo-input EXOR is realized as the TG with the extended set ofinput variables, , given by , w1= w2 = 1, , and threshold at 1.f x2 x1,( ) x1 x2⊕=xi i 1 … n, ,=( ), yn 1+( )w1 w2 … wn, , ,y 1= wixii 1=n∑ T≥ y 0=T 1 w1≤ x1 w2x2+ T 2< w1x1 w2x2+ T 1<T 2 w1≤ x1 w2x2+Figure 2.-(a) 2-input EXOR realized with a networks of TGs, (b)Bias scheme for nanopipeliningλ6 λ6 λ5λ4V bias1λ3 λ3 λ2λ1V bias1λ9λ9 λ8λ7V bias2V outx2x1x2x1λ2 λ1<λ1 λ2 λ3+<λ5 λ4<λ4 λ5 λ6+>λ4 λ5 2λ6+<λ7 λ8<λ7 λ9+ λ8>VBIASV bias1V bias2(a)(b)λ4 λ4λ3 λ3λ2λ1λ0x1 x2λ1 λ2 λ0< <λ2 λ3+ λ1 λ3 λ4+ +<λ2 λ3+ λ0<λ0 λ2 2λ3+<Figure 3.-2-input EXOR realized as an MTTG.V biasV outy1 y2 y3, ,{ } x1 x2 x1 x2∧, ,{ }w3 2–=Figure 5 shows a realization using the logic style proposedin [8] (GTG2). This realization is obtained since the 2-inputEXOR can be explained as a a TG over the extended set ofinput variables given by , w1 = 2,and threshold at 1. Note that the two upper inputbranches in Figure 4 have been combined.From the performance point of view, MOBILE TGs withonly negative weights (all input branches in parallel with driverRTD) are superior since transistors associated to positiveweights are larger to compensate reduced gate to source volt-ages, which increases capacitances. Thus, it would be desirableto obtain representations for the target functions with only neg-ative weights. In addition, having all branches in parallel couldenable additional combinations. We are able to obtain such arepresentation by applying a basic property of threshold func-tions which states that given a threshold function ,with weights wi, , and threshold T, the functionis also a threshold function with weights, , and . For our EXORexample, this means that it can be represented as a TG over theset of input variables, , given by ,and threshold at (applying the statedproperty to the represetation supporting GTG2). In addition, itcan be described as a TG with a single input variable, given by, , and threshold at. Figure 6 depicts the circuit realization obtained from thismodel (GTG3) [9]. Note that areas of driver and load RTDs areinterchanged with respect to GTG2 and that two inverters arerequired. Pipelined operation of cascaded GTG3 with theinverters which do not exist in previously reported MOBILEtopologies has been validated through extensive simulations ofseveral complex examples.In order to compare the circuit architectures we have carriedout simulations of three stage chains of the 2-input exor gatesin a non commercial university InP technology in which RTDand transistors can be co-integrated. For this RTD, Vp is 0.21V,the peak current density 21KA/cm2, the peak to valley currentratio is about 6.25 at room temperature and the capacitance is4fF/µm2. The transistor is a depletion HFET with threshold volt-age and minimum gate-length 0.6µm. Minimum gate-length transistors have been used. The sizes of the transistorshave been selected to optimize the operating frequency forclocked Vbias between 0V and 0.7V (high voltage levelVBIAS= 0.7V). In all the simulations, models for RTDs andtransistors experimentally validated have been used [10]. Inorder to accept as correct one simulation, the three gate out-puts are checked.Table I summarizes performance in terms offrequency and power-delay product obtained through simula-tions. Devices counts are reported too. Inverters required bythe topology proposed in this paper have been included in thesimulations.λ4 λ2λ1λ3λ3x2x1λ1 λ2<λ2 λ1 λ3+<λ2 λ4+ λ1 2λ3+>Figure 4.- 2-input EXOR from [7] (GTG1).V biasV outx1 x2∨ x1 x2∧,{ }w2 2–=λ3 λ2λ1λ3x2x1λ1 λ2<λ2 λ1 λ3+<Figure 5.- 2-input EXOR from [8] (GTG2)V biasV outf xn...x1( )1 i n≤ ≤f xn...x j...x1( )w'i wi= i j≠ w' j w j–= T ' T w j–=y1 y2,{ } x1 x2∨ x1 x2∧,{ }w1 w2 2–= = 1–y1{ } x1 x2∨( ) x1 x2∧( )∨{ } w1 2–=1–x1λ3λ2λ1x2λ1 λ2<λ2 λ1 λ3+<Figure 6.- 2-input EXOR from [9] (GTG3).V outV bias0.2V–In order to explore the application of the different describedthreshold based MOBILEs to logic design, we have designed n-bit adders using TGs, MTTGs and GTG3 exhibiting the bestperformance among the generalized TGs.III. DESIGN OF N-BIT ADDERSFigure 7, 8 and 9 show the logic diagram of nanopipelinedcarry propagation n-bit adders.Figure 7 depicts the logic diagram of the TG nanopipelined n-bit carry-propagation adder. The main difference between theTG adder proposed in [4] and the presented here consists on theuse of only negative weights in most of its gates, which hasadvantages in terms of speed. power and robutness.Figure 8 depicts the logic diagram of the MTTG nan-opipelined n-bit carry-propagation adder. Note that it usesmodified full adders in which complemented inputs areprocessed in some stages. Each of them consist on athreeinput-minority and a three-input EXNOR in two levels.The avoidance of using a three-input EXOR gate, as in thereported n-bit adder scheme [11], is due to its really poor fre-quency.The third design to be analized is the GTG3 nanopipelinedn-bit carry-propagation adder shown in Figure 9. In this casethe 3-input EXOR required for the FA is also implemented intwo levels. Although when using a single gate, the fre-quency does not degradate as much as in the MTTGdesign.Note that all the n-bits adders proposed require a two-levelnetwork for the full adder . This means the latency at the sameoperation frequency is the same for the three adders. Note thataditional buffers and inverters are required in the architec-tures to support pipeline.Eight-bit adders have been designed to operate up to 1.33GHzusing each of the architectures. Minimization of power has beenthe design target. Nanopipelined architectures for multipliersand divisors recently reported [12] can take advantage of theseadvanced proposed adders.Table I:  Simulation results for 2-input exor. PDP = (P@Fmax)/FmaxStyleFmax(GHz)PDP/PDPproposednºDevicesTGs 2.65 6.75 18MTTG 1.75 3.25 11GTG1 0.83 5.5 9GTG2 1.14 3.25 8GTG3(including inverters)4 1 11[111;2]A0B0A1B1C2 C’n-1 CnAn-1Bn-1[1-11;1]FASn-1FAFigure 7.- TG nanopipelined n-bit adder.C’1V biasyx1V biasx1x2x3V biasyx1x2 x3V biasyx1x2V biasyx1x2y[111;3][111;1][11;1][1-1;0]S1S’0[11;2]&exor[111;2]Modified FAA0B0A1B1S1C2An-1Bn-1Figure 8.- MTTG/TG nanopipelined n-bit adder.C’1V biasyx1x2V biasyx1V biasyx1x2V biasyx1x2x3exorexorS’0[111;2]Modified FASn-1CnC’n-1exorexorn evenn evenTable II summarizes a comparison between the three designs.For 8 bit adders operating at 1.33 GHz the design based inMTTGs has 14% more devices and consumes 35% morepower than the GTG3, on other hand the design based in TGshas 11% more devices and consumes 3% more power thanGTG3. The best result of speed corresponds to the GTG3 whichhas almost twice the maximum frequency exhibited by the TGadder design. Furthermore the power-delay product at maximumfrequency is better in GTG3 design.IV. CONCLUSIONSIn this paper different designs of nanopipelined 8-bitadder based on RTDs and HFET devices has been described.An extensive analysis of gates based on Threshold Logicconcept has concluded with the choice of the best designs interms of novelty, speed, power consumption and number ofdevices for the adder implementation. The selected gates arethe TGs, MTTGs and GTG3. A comparative analysis hasbeen carried between them. The proposed design with GTGshas demonstrated several advantages in comparison withTGs and MTTGs: higher speed, lower number of devices,and lower power consumption at the same operation fre-quency.REFERENCES[1] Maezawa, K., T. Akeyoshi, and T. Mizutani," Func-tions and applications of monostable-bistable transi-tion logic elements (MOBILE’s) having multiple-inputterminals". Transactions on Electron Devices, IEEE,1994. 41(2): p. 148-154[2] S. Muroga, Threshold Logic and Its Applications, NewYork: Wiley, 1971.[3] Akeyoshi, T., K. Maezawa, and T. Mizutani," Weight-ed sum threshold logic operation of MOBILE(monostable-bistable transition logic element) usingresonant-tunneling transistors". Electron Device Let-ters, IEEE, 1993. 14(10): p. 475-477[4] C. Pacha et al.: “Threshold Logic Circuit Design ofParallel Adders Using Resonant Tunnelling Devices,”IEEE Trans. on VLSI Systems, Vol. 8, no. 5, pp. 558-572, Oct. 2000.[5] W. Prost, S.O. Kim, P. Glosekotter, C. Pacha, H. vanHusen, T. Reiman, K.F. Goser and F.J. Tegude: “Ex-perimental Threshold Logic Implementations Basedon Resonnt Tunnelling Diodes”, International Confer-ence on Electronics Circuits and Systems, ICECS, pp.669-672, 2002[6] M.J. Avedillo, J.M: Quintana, H. Pettenghi, P.M.Kelly, and C.J. Thompson, “Multi-threshold Thresh-old Logic Circuit Design Using Resonant TunnelingDevices,” Electronics Letters, Vol. 39, pp. 1502-1504,2003.[7] P.M. Kelly, C.J. Thompson, T.M. McGinnity, and L.P.Maguire, “Investigation of a Programmable ThresholdLogic Gate Array,” Proc. Int. Conf. on Electronics,Circuits, and Systems (ICECS), pp. 673-676, 2002.[8] K. S. Berezowski: “Compact binary logic circuits de-sign using negative differential resistance devices”,Electronics Letters, Vol. 42, No. 16, August 2006.[9] H. Pettenghi, M.J. Avedillo, J.M Quintana, “A novelcontribution to the RTD-Based Threshold Logic Fam-ily”, International Symposium on Circuits and Sys-tems, 2008. ISCAS 2008. Accepted.[10] W. Prost et al.: EU IST Report LOCOM no. 28 844 Dec.2000.[11] Pettenghi, H., M.J. Avedillo, and J.M. Quintana," Nan-opipelined RTD adders using Multi-Threshold Thresh-old Gates". Proc. Design of Circuits and IntegratedSystems, 2005. DCIS 2005.[12] P. Gupta, N. K. Jha: “An Algorithm for Nano-pipelin-ing of Circuits and Architectures for a Nanotechnolo-gy”, Proceedings Design, Automation and Test in Eu-rope Conference, Vol. 2 pp. 904-909, 2004.Figure 9.-GTG3 nanopipelined n-bit adder.V biasx2x1x3yV biasyx1x2V biasyx1x2V biasyx1&exor[111;2]Modified FAA0B0A1B1S1C2An-1Bn-1C’1exorexorS’0[111;2]Modified FASn-1CnC’n-1exorexorn evenTable II. Comparison between 8-bit adders.DeviceCountFmax(GHz) P@Fmax(mW) P@1.33GHz(mW) PDP@Fmax(pJ)MTTG 599 1.89 16.82 15.43 8.90TG 584 1.67 11.90 11.82 7.13GTG3 605 3.13 15.20 11.47 4.86

RTD based logic circuits using generalized threshold gates

https://idus.us.es/bitstream/11441/77728/1/RTD%20based%20Logic.pdf

RTD based logic circuits using generalized threshold gates

Abstract

Similar works

Full text

Available Versions

idUS. Depósito de Investigación Universidad de Sevilla